[PATCH 1/3] add dma_coherent_write_sync to DMA API

[Catalin Marinas]

(coming late to this thread due to holidays)

2011/9/1 Mark Salter <msalter at redhat.com>:
> On Thu, 2011-09-01 at 11:57 +0200, Michał Mirosław wrote:
>> BTW, if there's no time limit on write buffers flushing, or if write
>> buffers can cause reordering of the writes, then the memory accesses
>> need to be managed just like non-DMA-coherent memory. So what differs
>> then in DMA-coherent vs non-DMA-coherent mappings then?
>
> My understanding is that ordering is preserved, but an ARM guy should
> probably verify that.

On ARMv6 onwards the coherent DMA is Normal Non-cacheable memory and
this is buffered and can be reordered.

-- 
Catalin