[PATCH v3 5/5] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
Dave Martin
dave.martin at linaro.org
Tue Nov 29 11:40:50 EST 2011
On Tue, Nov 29, 2011 at 03:11:13PM +0000, Pawel Moll wrote:
> This patch adds Device Trees for ARM Ltd. CoreTile Express A5x2
> and CoreTile Express A9x4 used with V2M motherboard and an initial
> implementation of the DT machine support (this code is separate
> from the current core tile code).
>
> Signed-off-by: Pawel Moll <pawel.moll at arm.com>
> ---
> arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 131 ++++++++++++++++++++++++++++
> arch/arm/boot/dts/vexpress-v2p-ca9.dts | 145 +++++++++++++++++++++++++++++++
> arch/arm/mach-vexpress/Kconfig | 23 +++++
> arch/arm/mach-vexpress/Makefile | 1 +
> arch/arm/mach-vexpress/v2p-ca5s_ca9.c | 115 ++++++++++++++++++++++++
> 5 files changed, 415 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
> create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c
>
> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> new file mode 100644
> index 0000000..e63c251
> --- /dev/null
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> @@ -0,0 +1,131 @@
> +/*
> + * ARM Ltd. Versatile Express
> + *
> + * CoreTile Express A5x2
> + * Cortex-A5 MPCore (V2P-CA5s)
> + *
> + * HBI-0225B
> + */
> +
> +/dts-v1/;
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + model = "V2P-CA5s";
> + arm,hbi = <0x225>;
> + compatible = "arm,vexpress-v2p-ca5s";
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + serial0 = &v2m_serial0;
> + serial1 = &v2m_serial1;
> + serial2 = &v2m_serial2;
> + serial3 = &v2m_serial3;
> + i2c0 = &v2m_i2c_dvi;
> + i2c1 = &v2m_i2c_pcie;
> + };
> +
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x40000000>;
> + };
> +
> + hdlcd at 2a110000 {
> + compatible = "arm,hdlcd";
> + reg = <0x2a110000 0x1000>;
> + interrupts = <0 85 4>;
> + };
> +
> + memory-controller at 2a150000 {
> + compatible = "arm,pl341", "arm,primecell";
> + reg = <0x2a150000 0x1000>;
> + };
> +
> + memory-controller at 2a190000 {
> + compatible = "arm,pl354", "arm,primecell";
> + reg = <0x2a190000 0x1000>;
> + interrupts = <0 86 4>,
> + <0 87 4>;
> + };
> +
> + gic: interrupt-controller at 2c001000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x2c001000 0x1000>,
> + <0x2c000100 0x100>;
> + };
> +
> + L2: cache-controller at 2c0f0000 {
> + compatible = "arm,pl310-cache";
> + reg = <0x2c0f0000 0x1000>;
> + interrupts = <0 84 4>;
> + cache-level = <2>;
> + arm,data-latency = <0>;
> + arm,tag-latency = <0>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a9-pmu";
> + interrupts = <0 68 4>,
> + <0 69 4>;
> + };
> +
> + motherboard {
> + ranges = <0 0 0x08000000 0x04000000>,
> + <1 0 0x14000000 0x04000000>,
> + <2 0 0x18000000 0x04000000>,
> + <3 0 0x1c000000 0x04000000>,
> + <4 0 0x0c000000 0x04000000>,
> + <5 0 0x10000000 0x04000000>;
> +
> + interrupt-map-mask = <0 0 63>;
> + interrupt-map = <0 0 0 &gic 0 0 4>,
> + <0 0 1 &gic 0 1 4>,
> + <0 0 2 &gic 0 2 4>,
> + <0 0 3 &gic 0 3 4>,
> + <0 0 4 &gic 0 4 4>,
> + <0 0 5 &gic 0 5 4>,
> + <0 0 6 &gic 0 6 4>,
> + <0 0 7 &gic 0 7 4>,
> + <0 0 8 &gic 0 8 4>,
> + <0 0 9 &gic 0 9 4>,
> + <0 0 10 &gic 0 10 4>,
> + <0 0 11 &gic 0 11 4>,
> + <0 0 12 &gic 0 12 4>,
> + <0 0 13 &gic 0 13 4>,
> + <0 0 14 &gic 0 14 4>,
> + <0 0 15 &gic 0 15 4>,
> + <0 0 16 &gic 0 16 4>,
> + <0 0 17 &gic 0 17 4>,
> + <0 0 18 &gic 0 18 4>,
> + <0 0 19 &gic 0 19 4>,
> + <0 0 20 &gic 0 20 4>,
> + <0 0 21 &gic 0 21 4>,
> + <0 0 22 &gic 0 22 4>,
> + <0 0 23 &gic 0 23 4>,
> + <0 0 24 &gic 0 24 4>,
> + <0 0 25 &gic 0 25 4>,
> + <0 0 26 &gic 0 26 4>,
> + <0 0 27 &gic 0 27 4>,
> + <0 0 28 &gic 0 28 4>,
> + <0 0 29 &gic 0 29 4>,
> + <0 0 30 &gic 0 30 4>,
> + <0 0 31 &gic 0 31 4>,
> + <0 0 32 &gic 0 32 4>,
> + <0 0 33 &gic 0 33 4>,
> + <0 0 34 &gic 0 34 4>,
> + <0 0 35 &gic 0 35 4>,
> + <0 0 36 &gic 0 36 4>,
> + <0 0 37 &gic 0 37 4>,
> + <0 0 38 &gic 0 38 4>,
> + <0 0 39 &gic 0 39 4>,
> + <0 0 40 &gic 0 40 4>,
> + <0 0 41 &gic 0 41 4>,
> + <0 0 42 &gic 0 42 4>;
> + };
> +};
> +
> +/include/ "vexpress-v2m-rs1.dtsi"
> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
> new file mode 100644
> index 0000000..c51fe09
> --- /dev/null
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
> @@ -0,0 +1,145 @@
> +/*
> + * ARM Ltd. Versatile Express
> + *
> + * CoreTile Express A9x4
> + * Cortex-A9 MPCore (V2P-CA9)
> + *
> + * HBI-0191B
> + */
> +
> +/dts-v1/;
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + model = "V2P-CA9";
> + arm,hbi = <0x191>;
> + compatible = "arm,vexpress-v2p-ca9";
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + serial0 = &v2m_serial0;
> + serial1 = &v2m_serial1;
> + serial2 = &v2m_serial2;
> + serial3 = &v2m_serial3;
> + i2c0 = &v2m_i2c_dvi;
> + i2c1 = &v2m_i2c_pcie;
> + };
> +
> + memory at 60000000 {
> + device_type = "memory";
> + reg = <0x60000000 0x40000000>;
> + };
> +
> + clcd at 10020000 {
> + compatible = "arm,pl111", "arm,primecell";
> + reg = <0x10020000 0x1000>;
> + interrupts = <0 44 4>;
> + };
> +
> + memory-controller at 100e0000 {
> + compatible = "arm,pl341", "arm,primecell";
> + reg = <0x100e0000 0x1000>;
> + };
> +
> + memory-controller at 100e1000 {
> + compatible = "arm,pl354", "arm,primecell";
> + reg = <0x100e1000 0x1000>;
> + interrupts = <0 45 4>,
> + <0 46 4>;
> + };
> +
> + timer at 100e4000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0x100e4000 0x1000>;
> + interrupts = <0 48 4>,
> + <0 49 4>;
> + };
> +
> + watchdog at 100e5000 {
> + compatible = "arm,sp805", "arm,primecell";
> + reg = <0x100e5000 0x1000>;
> + interrupts = <0 51 4>;
> + };
> +
> + gic: interrupt-controller at 1e001000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x1e001000 0x1000>,
> + <0x1e000100 0x100>;
> + };
> +
> + L2: cache-controller at 1e00a000 {
> + compatible = "arm,pl310-cache";
> + reg = <0x1e00a000 0x1000>;
> + interrupts = <0 43 4>;
> + cache-level = <2>;
> + arm,data-latency = <0>;
> + arm,tag-latency = <0>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a9-pmu";
> + interrupts = <0 60 4>,
> + <0 61 4>,
> + <0 62 4>,
> + <0 63 4>;
> + };
> +
> + motherboard {
> + ranges = <0 0 0x40000000 0x04000000>,
> + <1 0 0x44000000 0x04000000>,
> + <2 0 0x48000000 0x04000000>,
> + <3 0 0x4c000000 0x04000000>,
> + <7 0 0x10000000 0x00020000>;
> +
> + interrupt-map-mask = <0 0 63>;
> + interrupt-map = <0 0 0 &gic 0 0 4>,
> + <0 0 1 &gic 0 1 4>,
> + <0 0 2 &gic 0 2 4>,
> + <0 0 3 &gic 0 3 4>,
> + <0 0 4 &gic 0 4 4>,
> + <0 0 5 &gic 0 5 4>,
> + <0 0 6 &gic 0 6 4>,
> + <0 0 7 &gic 0 7 4>,
> + <0 0 8 &gic 0 8 4>,
> + <0 0 9 &gic 0 9 4>,
> + <0 0 10 &gic 0 10 4>,
> + <0 0 11 &gic 0 11 4>,
> + <0 0 12 &gic 0 12 4>,
> + <0 0 13 &gic 0 13 4>,
> + <0 0 14 &gic 0 14 4>,
> + <0 0 15 &gic 0 15 4>,
> + <0 0 16 &gic 0 16 4>,
> + <0 0 17 &gic 0 17 4>,
> + <0 0 18 &gic 0 18 4>,
> + <0 0 19 &gic 0 19 4>,
> + <0 0 20 &gic 0 20 4>,
> + <0 0 21 &gic 0 21 4>,
> + <0 0 22 &gic 0 22 4>,
> + <0 0 23 &gic 0 23 4>,
> + <0 0 24 &gic 0 24 4>,
> + <0 0 25 &gic 0 25 4>,
> + <0 0 26 &gic 0 26 4>,
> + <0 0 27 &gic 0 27 4>,
> + <0 0 28 &gic 0 28 4>,
> + <0 0 29 &gic 0 29 4>,
> + <0 0 30 &gic 0 30 4>,
> + <0 0 31 &gic 0 31 4>,
> + <0 0 32 &gic 0 32 4>,
> + <0 0 33 &gic 0 33 4>,
> + <0 0 34 &gic 0 34 4>,
> + <0 0 35 &gic 0 35 4>,
> + <0 0 36 &gic 0 36 4>,
> + <0 0 37 &gic 0 37 4>,
> + <0 0 38 &gic 0 38 4>,
> + <0 0 39 &gic 0 39 4>,
> + <0 0 40 &gic 0 40 4>,
> + <0 0 41 &gic 0 41 4>,
> + <0 0 42 &gic 0 42 4>;
> + };
> +};
> +
> +/include/ "vexpress-v2m.dtsi"
> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> index 2180888..9eb8161 100644
> --- a/arch/arm/mach-vexpress/Kconfig
> +++ b/arch/arm/mach-vexpress/Kconfig
> @@ -23,4 +23,27 @@ config ARCH_VEXPRESS_RS1
> RS1 VE memory map (i.a. motherboard peripherals at
> 0x1c000000, RAM at 0x80000000).
>
> +config ARCH_VEXPRESS_V2P_CA5S_CA9
> + bool "CoreTile Express A5x2 and A9x4 based platform support"
> + select CPU_V7
> + select ARM_GIC
> + select ARCH_VEXPRESS_RS1
> + select ARCH_VEXPRESS_DT
> + select ARM_ERRATA_720789
> + select ARM_ERRATA_751472
> + select PL310_ERRATA_753970 if CACHE_PL310
The config option for L2x0/PL310 doesn't get selected for this platform.
Rather than bloat the list in arch/arm/mm/Kconfig each time we add a
coretile (and get a merge conflict with anyone else adding a platform
with an L2CC) I've posted a patch to attempt to factorise that:
ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable
If this looks OK and nobody objects, I suggest to build on top of that.
Note that select PL310_ERRATA_753970 if CACHE_PL310 also needs to be
propagated to ARCH_VEXPRESS_CA9X4. Maybe we should have a common symbol
which selects/depends on the common stuff instead of duplicating it for
every coretile -- they will tend to get out of sync.
Cheers
---Dave
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