[PATCH 5/5] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4

[Pawel Moll]

> > +     dmc at 2a150000 {
> I missed this earlier, but the preferred generic name is
> "memory-controller"
> > +     smc at 2a190000 {
> same here.
>
Ok.

> > +config ARCH_VEXPRESS_V2P_CA5S_CA9
>
> You don't expect this to expand to A7 or A15?

A7/A15's SCUs are CP15 devices, not memory mapped ones. The same with
timers - A9-like TWD is no more, "taken over" by architected timers.
It's a different initialisation and SMP code, essentially. I wish it
wasn't... Also, in future I may be working on adding support for
MMU-less R-Class processors, which are going to be very very
different ;-)

Cheers!

Paweł

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.