Common clock and dvfs
ccross at google.com
Thu May 5 02:50:52 EDT 2011
On Wed, May 4, 2011 at 11:35 PM, Paul Walmsley <paul at pwsan.com> wrote:
> On Wed, 4 May 2011, Colin Cross wrote:
>> Imagine a chip where a clock can feed devices A, B, and C. If the
>> devices are always clocked at the same rate, and can't gate their
>> clocks, the minimum voltage that can be applied to a rail is
>> determined ONLY by the rate of the clock.
> That's not so -- although admittedly it's a side issue, and not
> particularly related to DVFS.
> For example, the device may have some external I/O lines which need to be
> at least some minimum voltage level for the externally-connected device to
> function. This minimum voltage level can be unrelated to the device's
> clock frequency.
True, that was an oversimplificaiton. I meant the minimum voltage that
scales with clock frequencies only depends on the clock frequency, not
the device. Devices do need to be able to specify a higher minimum
voltage, and the regulator api needs to handle it.
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