[PATCH 1/4] drivers: create a pinmux subsystem
tony at atomide.com
Wed May 4 05:22:19 EDT 2011
* Colin Cross <ccross at google.com> [110502 14:26]:
> On Mon, May 2, 2011 at 1:52 PM, Stephen Warren <swarren at nvidia.com> wrote:
> * Drive strength is also controlled through groups of pins, but
> different groups than pinmux. Most of the drive strength groups are
> collections of pad mux groups, but there are a few pins that are in
> the same pad mux group but a different drive strength group.
> * Setting a pin as a GPIO overrides its group's mux setting, except
> for the group's tristate. You must untristate the entire group to use
> a single pin as a GPIO.
> * Each group has a "safe mode", but which mux id to select to enter
> the safe mode is completely random.
Just posted something in this thread regarding using standard data and
standard read and write functions, then allow setting platform specific
custom flags as needed. Care to see if that works for you too?
> In the end, we determined that there was no way to sanely handle
> setting up Tegra's pinmux programatically, and instead required each
> board to pass in a table of pinmux settings.
Eventually we should get the package specific table of available pins
and the board specific settings in devicetree data. And then it's
easy to set the pins as desired while being able to debug it.
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