No subject
Mon Jun 27 16:47:34 EDT 2011
- Added 'notrace' to all _read_sched_lock() functions, fixing
the ftrace problem reported by Jamie Iles
- Removed useless #include <linux/sched.h> from touched files
- Made omap_32k_read_sched_clock() static
arch/arm/include/asm/sched_clock.h | 108 +-------------------------=
----
arch/arm/kernel/sched_clock.c | 97 +++++++++++++++++++++++++-=
-
arch/arm/mach-ixp4xx/common.c | 16 +----
arch/arm/mach-mmp/time.c | 16 +----
arch/arm/mach-omap1/time.c | 58 +---------------
arch/arm/mach-omap2/timer.c | 20 +-----
arch/arm/mach-pxa/time.c | 15 +---
arch/arm/mach-sa1100/time.c | 28 +-------
arch/arm/mach-tegra/timer.c | 24 +------
arch/arm/mach-u300/timer.c | 15 +---
arch/arm/plat-iop/time.c | 16 +----
arch/arm/plat-mxc/time.c | 15 +---
arch/arm/plat-nomadik/timer.c | 18 +----
arch/arm/plat-omap/counter_32k.c | 40 +----------
arch/arm/plat-omap/include/plat/common.h | 1 -
arch/arm/plat-orion/time.c | 21 +-----
arch/arm/plat-s5p/s5p-time.c | 19 +-----
arch/arm/plat-versatile/sched-clock.c | 29 ++------
18 files changed, 141 insertions(+), 415 deletions(-)
diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sche=
d_clock.h
index c8e6ddf..e3f7572 100644
--- a/arch/arm/include/asm/sched_clock.h
+++ b/arch/arm/include/asm/sched_clock.h
@@ -8,113 +8,7 @@
#ifndef ASM_SCHED_CLOCK
#define ASM_SCHED_CLOCK
=20
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-struct clock_data {
-=09u64 epoch_ns;
-=09u32 epoch_cyc;
-=09u32 epoch_cyc_copy;
-=09u32 mult;
-=09u32 shift;
-};
-
-#define DEFINE_CLOCK_DATA(name)=09struct clock_data name
-
-static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift)
-{
-=09return (cyc * mult) >> shift;
-}
-
-/*
- * Atomically update the sched_clock epoch. Your update callback will
- * be called from a timer before the counter wraps - read the current
- * counter value, and call this function to safely move the epochs
- * forward. Only use this from the update callback.
- */
-static inline void update_sched_clock(struct clock_data *cd, u32 cyc, u32 =
mask)
-{
-=09unsigned long flags;
-=09u64 ns =3D cd->epoch_ns +
-=09=09cyc_to_ns((cyc - cd->epoch_cyc) & mask, cd->mult, cd->shift);
-
-=09/*
-=09 * Write epoch_cyc and epoch_ns in a way that the update is
-=09 * detectable in cyc_to_fixed_sched_clock().
-=09 */
-=09raw_local_irq_save(flags);
-=09cd->epoch_cyc =3D cyc;
-=09smp_wmb();
-=09cd->epoch_ns =3D ns;
-=09smp_wmb();
-=09cd->epoch_cyc_copy =3D cyc;
-=09raw_local_irq_restore(flags);
-}
-
-/*
- * If your clock rate is known at compile time, using this will allow
- * you to optimize the mult/shift loads away. This is paired with
- * init_fixed_sched_clock() to ensure that your mult/shift are correct.
- */
-static inline unsigned long long cyc_to_fixed_sched_clock(struct clock_dat=
a *cd,
-=09u32 cyc, u32 mask, u32 mult, u32 shift)
-{
-=09u64 epoch_ns;
-=09u32 epoch_cyc;
-
-=09/*
-=09 * Load the epoch_cyc and epoch_ns atomically. We do this by
-=09 * ensuring that we always write epoch_cyc, epoch_ns and
-=09 * epoch_cyc_copy in strict order, and read them in strict order.
-=09 * If epoch_cyc and epoch_cyc_copy are not equal, then we're in
-=09 * the middle of an update, and we should repeat the load.
-=09 */
-=09do {
-=09=09epoch_cyc =3D cd->epoch_cyc;
-=09=09smp_rmb();
-=09=09epoch_ns =3D cd->epoch_ns;
-=09=09smp_rmb();
-=09} while (epoch_cyc !=3D cd->epoch_cyc_copy);
-
-=09return epoch_ns + cyc_to_ns((cyc - epoch_cyc) & mask, mult, shift);
-}
-
-/*
- * Otherwise, you need to use this, which will obtain the mult/shift
- * from the clock_data structure. Use init_sched_clock() with this.
- */
-static inline unsigned long long cyc_to_sched_clock(struct clock_data *cd,
-=09u32 cyc, u32 mask)
-{
-=09return cyc_to_fixed_sched_clock(cd, cyc, mask, cd->mult, cd->shift);
-}
-
-/*
- * Initialize the clock data - calculate the appropriate multiplier
- * and shift. Also setup a timer to ensure that the epoch is refreshed
- * at the appropriate time interval, which will call your update
- * handler.
- */
-void init_sched_clock(struct clock_data *, void (*)(void),
-=09unsigned int, unsigned long);
-
-/*
- * Use this initialization function rather than init_sched_clock() if
- * you're using cyc_to_fixed_sched_clock, which will warn if your
- * constants are incorrect.
- */
-static inline void init_fixed_sched_clock(struct clock_data *cd,
-=09void (*update)(void), unsigned int bits, unsigned long rate,
-=09u32 mult, u32 shift)
-{
-=09init_sched_clock(cd, update, bits, rate);
-=09if (cd->mult !=3D mult || cd->shift !=3D shift) {
-=09=09pr_crit("sched_clock: wrong multiply/shift: %u>>%u vs calculated %u>=
>%u\n"
-=09=09=09"sched_clock: fix multiply/shift to avoid scheduler hiccups\n",
-=09=09=09mult, shift, cd->mult, cd->shift);
-=09}
-}
-
extern void sched_clock_postinit(void);
+extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long r=
ate);
=20
#endif
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
index 9a46370..3c0d93a 100644
--- a/arch/arm/kernel/sched_clock.c
+++ b/arch/arm/kernel/sched_clock.c
@@ -14,25 +14,88 @@
=20
#include <asm/sched_clock.h>
=20
+struct clock_data {
+=09u64 epoch_ns;
+=09u32 epoch_cyc;
+=09u32 epoch_cyc_copy;
+=09u32 mult;
+=09u32 shift;
+};
+
static void sched_clock_poll(unsigned long wrap_ticks);
static DEFINE_TIMER(sched_clock_timer, sched_clock_poll, 0, 0);
-static void (*sched_clock_update_fn)(void);
+
+static struct clock_data cd;
+static u32 sched_clock_mask;
+static u32 __read_mostly (*read_sched_clock)(void);
+
+static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift)
+{
+=09return (cyc * mult) >> shift;
+}
+
+static unsigned long long cyc_to_sched_clock(struct clock_data *cd,
+=09=09=09=09=09 u32 cyc, u32 mask)
+{
+=09u64 epoch_ns;
+=09u32 epoch_cyc;
+
+=09/*
+=09 * Load the epoch_cyc and epoch_ns atomically. We do this by
+=09 * ensuring that we always write epoch_cyc, epoch_ns and
+=09 * epoch_cyc_copy in strict order, and read them in strict order.
+=09 * If epoch_cyc and epoch_cyc_copy are not equal, then we're in
+=09 * the middle of an update, and we should repeat the load.
+=09 */
+=09do {
+=09=09epoch_cyc =3D cd->epoch_cyc;
+=09=09smp_rmb();
+=09=09epoch_ns =3D cd->epoch_ns;
+=09=09smp_rmb();
+=09} while (epoch_cyc !=3D cd->epoch_cyc_copy);
+
+=09return epoch_ns + cyc_to_ns((cyc - epoch_cyc) & mask, cd->mult, cd->shi=
ft);
+}
+
+/*
+ * Atomically update the sched_clock epoch.
+ */
+static void notrace update_sched_clock(void)
+{
+=09unsigned long flags;
+=09u32 cyc;
+=09u64 ns;
+
+=09cyc =3D read_sched_clock();
+=09ns =3D cd.epoch_ns +
+=09=09cyc_to_ns((cyc - cd.epoch_cyc) & sched_clock_mask,
+=09=09=09 cd.mult, cd.shift);
+=09/*
+=09 * Write epoch_cyc and epoch_ns in a way that the update is
+=09 * detectable in cyc_to_fixed_sched_clock().
+=09 */
+=09raw_local_irq_save(flags);
+=09cd.epoch_cyc =3D cyc;
+=09smp_wmb();
+=09cd.epoch_ns =3D ns;
+=09smp_wmb();
+=09cd.epoch_cyc_copy =3D cyc;
+=09raw_local_irq_restore(flags);
+}
=20
static void sched_clock_poll(unsigned long wrap_ticks)
{
=09mod_timer(&sched_clock_timer, round_jiffies(jiffies + wrap_ticks));
-=09sched_clock_update_fn();
+=09update_sched_clock();
}
=20
-void __init init_sched_clock(struct clock_data *cd, void (*update)(void),
-=09unsigned int clock_bits, unsigned long rate)
+static void __init init_sched_clock(struct clock_data *cd,
+=09=09=09=09 unsigned int clock_bits, unsigned long rate)
{
=09unsigned long r, w;
=09u64 res, wrap;
=09char r_unit;
=20
-=09sched_clock_update_fn =3D update;
-
=09/* calculate the mult/shift to convert counter ticks to ns. */
=09clocks_calc_mult_shift(&cd->mult, &cd->shift, rate, NSEC_PER_SEC, 0);
=20
@@ -60,7 +123,7 @@ void __init init_sched_clock(struct clock_data *cd, void=
(*update)(void),
=09 * sets the initial epoch.
=09 */
=09sched_clock_timer.data =3D msecs_to_jiffies(w - (w / 10));
-=09update();
+=09update_sched_clock();
=20
=09/*
=09 * Ensure that sched_clock() starts off at 0ns
@@ -68,6 +131,26 @@ void __init init_sched_clock(struct clock_data *cd, voi=
d (*update)(void),
=09cd->epoch_ns =3D 0;
}
=20
+unsigned long long notrace sched_clock(void)
+{
+=09if (read_sched_clock) {
+=09=09u32 cyc =3D read_sched_clock();
+=09=09return cyc_to_sched_clock(&cd, cyc, sched_clock_mask);
+=09}
+
+=09return (unsigned long long)(jiffies - INITIAL_JIFFIES)
+=09=09=09=09=09* (NSEC_PER_SEC / HZ);
+}
+
+void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long r=
ate)
+{
+=09BUG_ON(bits > 32);
+=09read_sched_clock =3D read;
+=09sched_clock_mask =3D (1 << bits) - 1;
+=09init_sched_clock(&cd, bits, rate);
+=09pr_debug("Registered %pF as sched_clock source\n", read);
+}
+
void __init sched_clock_postinit(void)
{
=09sched_clock_poll(sched_clock_timer.data);
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 0777257..d10d838 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -17,7 +17,6 @@
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/serial.h>
-#include <linux/sched.h>
#include <linux/tty.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
@@ -402,18 +401,9 @@ void __init ixp4xx_sys_init(void)
/*
* sched_clock()
*/
-static DEFINE_CLOCK_DATA(cd);
-
-unsigned long long notrace sched_clock(void)
+static u32 notrace ixp4xx_read_sched_clock(void)
{
-=09u32 cyc =3D *IXP4XX_OSTS;
-=09return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-
-static void notrace ixp4xx_update_sched_clock(void)
-{
-=09u32 cyc =3D *IXP4XX_OSTS;
-=09update_sched_clock(&cd, cyc, (u32)~0);
+=09return *IXP4XX_OSTS;
}
=20
/*
@@ -429,7 +419,7 @@ unsigned long ixp4xx_timer_freq =3D IXP4XX_TIMER_FREQ;
EXPORT_SYMBOL(ixp4xx_timer_freq);
static void __init ixp4xx_clocksource_init(void)
{
-=09init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq)=
;
+=09setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
=20
=09clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
=09=09=09ixp4xx_clocksource_read);
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 99833b9..fb730f4 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -25,7 +25,6 @@
=20
#include <linux/io.h>
#include <linux/irq.h>
-#include <linux/sched.h>
=20
#include <asm/sched_clock.h>
#include <mach/addr-map.h>
@@ -42,8 +41,6 @@
#define MAX_DELTA=09=09(0xfffffffe)
#define MIN_DELTA=09=09(16)
=20
-static DEFINE_CLOCK_DATA(cd);
-
/*
* FIXME: the timer needs some delay to stablize the counter capture
*/
@@ -59,16 +56,9 @@ static inline uint32_t timer_read(void)
=09return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(0));
}
=20
-unsigned long long notrace sched_clock(void)
+static u32 notrace mmp_read_sched_clock(void)
{
-=09u32 cyc =3D timer_read();
-=09return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-
-static void notrace mmp_update_sched_clock(void)
-{
-=09u32 cyc =3D timer_read();
-=09update_sched_clock(&cd, cyc, (u32)~0);
+=09return timer_read();
}
=20
static irqreturn_t timer_interrupt(int irq, void *dev_id)
@@ -175,7 +165,7 @@ void __init timer_init(int irq)
{
=09timer_config();
=20
-=09init_sched_clock(&cd, mmp_update_sched_clock, 32, CLOCK_TICK_RATE);
+=09setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE);
=20
=09ckevt.mult =3D div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
=09ckevt.max_delta_ns =3D clockevent_delta2ns(MAX_DELTA, &ckevt);
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index a183777..92b5847 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -37,7 +37,6 @@
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
-#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/clk.h>
#include <linux/err.h>
@@ -190,30 +189,9 @@ static __init void omap_init_mpu_timer(unsigned long r=
ate)
* -----------------------------------------------------------------------=
----
*/
=20
-static DEFINE_CLOCK_DATA(cd);
-
-static inline unsigned long long notrace _omap_mpu_sched_clock(void)
-{
-=09u32 cyc =3D ~omap_mpu_timer_read(1);
-=09return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-
-#ifndef CONFIG_OMAP_32K_TIMER
-unsigned long long notrace sched_clock(void)
-{
-=09return _omap_mpu_sched_clock();
-}
-#else
-static unsigned long long notrace omap_mpu_sched_clock(void)
-{
-=09return _omap_mpu_sched_clock();
-}
-#endif
-
-static void notrace mpu_update_sched_clock(void)
+static u32 notrace omap_mpu_read_sched_clock(void)
{
-=09u32 cyc =3D ~omap_mpu_timer_read(1);
-=09update_sched_clock(&cd, cyc, (u32)~0);
+=09return ~omap_mpu_timer_read(1);
}
=20
static void __init omap_init_clocksource(unsigned long rate)
@@ -223,7 +201,7 @@ static void __init omap_init_clocksource(unsigned long =
rate)
=09=09=09"%s: can't register clocksource!\n";
=20
=09omap_mpu_timer_start(1, ~0, 1);
-=09init_sched_clock(&cd, mpu_update_sched_clock, 32, rate);
+=09setup_sched_clock(omap_mpu_read_sched_clock, 32, rate);
=20
=09if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate,
=09=09=09300, 32, clocksource_mmio_readl_down))
@@ -254,30 +232,6 @@ static inline void omap_mpu_timer_init(void)
}
#endif=09/* CONFIG_OMAP_MPU_TIMER */
=20
-#if defined(CONFIG_OMAP_MPU_TIMER) && defined(CONFIG_OMAP_32K_TIMER)
-static unsigned long long (*preferred_sched_clock)(void);
-
-unsigned long long notrace sched_clock(void)
-{
-=09if (!preferred_sched_clock)
-=09=09return 0;
-
-=09return preferred_sched_clock();
-}
-
-static inline void preferred_sched_clock_init(bool use_32k_sched_clock)
-{
-=09if (use_32k_sched_clock)
-=09=09preferred_sched_clock =3D omap_32k_sched_clock;
-=09else
-=09=09preferred_sched_clock =3D omap_mpu_sched_clock;
-}
-#else
-static inline void preferred_sched_clock_init(bool use_32k_sched_clcok)
-{
-}
-#endif
-
static inline int omap_32k_timer_usable(void)
{
=09int res =3D false;
@@ -299,12 +253,8 @@ static inline int omap_32k_timer_usable(void)
*/
static void __init omap1_timer_init(void)
{
-=09if (omap_32k_timer_usable()) {
-=09=09preferred_sched_clock_init(1);
-=09} else {
+=09if (!omap_32k_timer_usable())
=09=09omap_mpu_timer_init();
-=09=09preferred_sched_clock_init(0);
-=09}
}
=20
struct sys_timer omap1_timer =3D {
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index e964072..24fb13d 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -248,7 +248,6 @@ static struct omap_dm_timer clksrc;
/*
* clocksource
*/
-static DEFINE_CLOCK_DATA(cd);
static cycle_t clocksource_read_cycles(struct clocksource *cs)
{
=09return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
@@ -262,23 +261,12 @@ static struct clocksource clocksource_gpt =3D {
=09.flags=09=09=3D CLOCK_SOURCE_IS_CONTINUOUS,
};
=20
-static void notrace dmtimer_update_sched_clock(void)
+static u32 notrace dmtimer_read_sched_clock(void)
{
-=09u32 cyc;
-
-=09cyc =3D __omap_dm_timer_read_counter(clksrc.io_base, 1);
-
-=09update_sched_clock(&cd, cyc, (u32)~0);
-}
-
-unsigned long long notrace sched_clock(void)
-{
-=09u32 cyc =3D 0;
-
=09if (clksrc.reserved)
-=09=09cyc =3D __omap_dm_timer_read_counter(clksrc.io_base, 1);
+=09=09return __omap_dm_timer_read_counter(clksrc.io_base, 1);
=20
-=09return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+=09return 0;
}
=20
/* Setup free-running counter for clocksource */
@@ -294,7 +282,7 @@ static void __init omap2_gp_clocksource_init(int gptime=
r_id,
=09=09gptimer_id, clksrc.rate);
=20
=09__omap_dm_timer_load_start(clksrc.io_base, OMAP_TIMER_CTRL_ST, 0, 1);
-=09init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
+=09setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
=20
=09if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
=09=09pr_err("Could not register clocksource %s\n",
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index de68470..b503049 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -16,7 +16,6 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
-#include <linux/sched.h>
=20
#include <asm/div64.h>
#include <asm/mach/irq.h>
@@ -32,18 +31,10 @@
* long as there is always less than 582 seconds between successive
* calls to sched_clock() which should always be the case in practice.
*/
-static DEFINE_CLOCK_DATA(cd);
=20
-unsigned long long notrace sched_clock(void)
+static u32 notrace pxa_read_sched_clock(void)
{
-=09u32 cyc =3D OSCR;
-=09return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-
-static void notrace pxa_update_sched_clock(void)
-{
-=09u32 cyc =3D OSCR;
-=09update_sched_clock(&cd, cyc, (u32)~0);
+=09return OSCR;
}
=20
=20
@@ -119,7 +110,7 @@ static void __init pxa_timer_init(void)
=09OIER =3D 0;
=09OSSR =3D OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
=20
-=09init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate);
+=09setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
=20
=09clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
=09ckevt_pxa_osmr0.max_delta_ns =3D
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index fa66024..1ee6d4c 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -12,7 +12,6 @@
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
-#include <linux/sched.h>=09/* just for sched_clock() - funny that */
#include <linux/timex.h>
#include <linux/clockchips.h>
=20
@@ -20,29 +19,9 @@
#include <asm/sched_clock.h>
#include <mach/hardware.h>
=20
-/*
- * This is the SA11x0 sched_clock implementation.
- */
-static DEFINE_CLOCK_DATA(cd);
-
-/*
- * Constants generated by clocks_calc_mult_shift(m, s, 3.6864MHz,
- * NSEC_PER_SEC, 60).
- * This gives a resolution of about 271ns and a wrap period of about 19min=
.
- */
-#define SC_MULT=09=092275555556u
-#define SC_SHIFT=0923
-
-unsigned long long notrace sched_clock(void)
-{
-=09u32 cyc =3D OSCR;
-=09return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
-}
-
-static void notrace sa1100_update_sched_clock(void)
+static u32 notrace sa100_read_sched_clock(void)
{
-=09u32 cyc =3D OSCR;
-=09update_sched_clock(&cd, cyc, (u32)~0);
+=09return OSCR;
}
=20
#define MIN_OSCR_DELTA 2
@@ -109,8 +88,7 @@ static void __init sa1100_timer_init(void)
=09OIER =3D 0;
=09OSSR =3D OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
=20
-=09init_fixed_sched_clock(&cd, sa1100_update_sched_clock, 32,
-=09=09=09 3686400, SC_MULT, SC_SHIFT);
+=09setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
=20
=09clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4);
=09ckevt_sa1100_osmr0.max_delta_ns =3D
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 9035042..b5dc8d2 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -19,7 +19,6 @@
=20
#include <linux/init.h>
#include <linux/err.h>
-#include <linux/sched.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
@@ -106,25 +105,9 @@ static struct clock_event_device tegra_clockevent =3D =
{
=09.set_mode=09=3D tegra_timer_set_mode,
};
=20
-static DEFINE_CLOCK_DATA(cd);
-
-/*
- * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC,=
60).
- * This gives a resolution of about 1us and a wrap period of about 1h11min=
.
- */
-#define SC_MULT=09=094194304000u
-#define SC_SHIFT=0922
-
-unsigned long long notrace sched_clock(void)
-{
-=09u32 cyc =3D timer_readl(TIMERUS_CNTR_1US);
-=09return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
-}
-
-static void notrace tegra_update_sched_clock(void)
+static u32 notrace tegra_read_sched_clock(void)
{
-=09u32 cyc =3D timer_readl(TIMERUS_CNTR_1US);
-=09update_sched_clock(&cd, cyc, (u32)~0);
+=09return timer_readl(TIMERUS_CNTR_1US);
}
=20
/*
@@ -218,8 +201,7 @@ static void __init tegra_init_timer(void)
=09=09WARN(1, "Unknown clock rate");
=09}
=20
-=09init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32,
-=09=09=09 1000000, SC_MULT, SC_SHIFT);
+=09setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
=20
=09if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
=09=09"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 5f51bde..bc1c789 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -9,7 +9,6 @@
* Author: Linus Walleij <linus.walleij at stericsson.com>
*/
#include <linux/interrupt.h>
-#include <linux/sched.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/clockchips.h>
@@ -337,18 +336,10 @@ static struct irqaction u300_timer_irq =3D {
* this wraps around for now, since it is just a relative time
* stamp. (Inspired by OMAP implementation.)
*/
-static DEFINE_CLOCK_DATA(cd);
=20
-unsigned long long notrace sched_clock(void)
+static u32 notrace u300_read_sched_clock(void)
{
-=09u32 cyc =3D readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
-=09return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-
-static void notrace u300_update_sched_clock(void)
-{
-=09u32 cyc =3D readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
-=09update_sched_clock(&cd, cyc, (u32)~0);
+=09return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
}
=20
=20
@@ -366,7 +357,7 @@ static void __init u300_timer_init(void)
=09clk_enable(clk);
=09rate =3D clk_get_rate(clk);
=20
-=09init_sched_clock(&cd, u300_update_sched_clock, 32, rate);
+=09setup_sched_clock(u300_read_sched_clock, 32, rate);
=20
=09/*
=09 * Disable the "OS" and "DD" timers - these are designed for Symbian!
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 7cdc516..fd94c55 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -18,7 +18,6 @@
#include <linux/time.h>
#include <linux/init.h>
#include <linux/timex.h>
-#include <linux/sched.h>
#include <linux/io.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
@@ -51,21 +50,12 @@ static struct clocksource iop_clocksource =3D {
=09.flags=09=09=3D CLOCK_SOURCE_IS_CONTINUOUS,
};
=20
-static DEFINE_CLOCK_DATA(cd);
-
/*
* IOP sched_clock() implementation via its clocksource.
*/
-unsigned long long notrace sched_clock(void)
+static u32 notrace iop_read_sched_clock(void)
{
-=09u32 cyc =3D 0xffffffffu - read_tcr1();
-=09return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-
-static void notrace iop_update_sched_clock(void)
-{
-=09u32 cyc =3D 0xffffffffu - read_tcr1();
-=09update_sched_clock(&cd, cyc, (u32)~0);
+=09return 0xffffffffu - read_tcr1();
}
=20
/*
@@ -151,7 +141,7 @@ void __init iop_init_time(unsigned long tick_rate)
{
=09u32 timer_ctl;
=20
-=09init_sched_clock(&cd, iop_update_sched_clock, 32, tick_rate);
+=09setup_sched_clock(iop_read_sched_clock, 32, tick_rate);
=20
=09ticks_per_jiffy =3D DIV_ROUND_CLOSEST(tick_rate, HZ);
=09iop_tick_rate =3D tick_rate;
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 4b0fe28..1c96cdb 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -108,18 +108,9 @@ static void gpt_irq_acknowledge(void)
=20
static void __iomem *sched_clock_reg;
=20
-static DEFINE_CLOCK_DATA(cd);
-unsigned long long notrace sched_clock(void)
+static u32 notrace mxc_read_sched_clock(void)
{
-=09cycle_t cyc =3D sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
-
-=09return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-
-static void notrace mxc_update_sched_clock(void)
-{
-=09cycle_t cyc =3D sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
-=09update_sched_clock(&cd, cyc, (u32)~0);
+=09return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
}
=20
static int __init mxc_clocksource_init(struct clk *timer_clk)
@@ -129,7 +120,7 @@ static int __init mxc_clocksource_init(struct clk *time=
r_clk)
=20
=09sched_clock_reg =3D reg;
=20
-=09init_sched_clock(&cd, mxc_update_sched_clock, 32, c);
+=09setup_sched_clock(mxc_read_sched_clock, 32, c);
=09return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
=09=09=09clocksource_mmio_readl_up);
}
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index ef74e15..7a0a9d7 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -17,7 +17,6 @@
#include <linux/clk.h>
#include <linux/jiffies.h>
#include <linux/err.h>
-#include <linux/sched.h>
#include <asm/mach/time.h>
#include <asm/sched_clock.h>
=20
@@ -30,23 +29,12 @@ void __iomem *mtu_base; /* Assigned by machine code */
* local implementation which uses the clocksource to get some
* better resolution when scheduling the kernel.
*/
-static DEFINE_CLOCK_DATA(cd);
-
-unsigned long long notrace sched_clock(void)
+static u32 notrace nomadik_read_sched_clock(void)
{
-=09u32 cyc;
-
=09if (unlikely(!mtu_base))
=09=09return 0;
=20
-=09cyc =3D -readl(mtu_base + MTU_VAL(0));
-=09return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-
-static void notrace nomadik_update_sched_clock(void)
-{
-=09u32 cyc =3D -readl(mtu_base + MTU_VAL(0));
-=09update_sched_clock(&cd, cyc, (u32)~0);
+=09return -readl(mtu_base + MTU_VAL(0));
}
=20
/* Clockevent device: use one-shot mode */
@@ -154,7 +142,7 @@ void __init nmdk_timer_init(void)
=09=09pr_err("timer: failed to initialize clock source %s\n",
=09=09 "mtu_0");
=20
-=09init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate);
+=09setup_sched_clock(nomadik_setup_sched_clock, 32, rate);
=20
=09/* Timer 1 is used for events */
=20
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_=
32k.c
index a6cbb71..5f0f229 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -17,7 +17,6 @@
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <linux/sched.h>
#include <linux/clocksource.h>
=20
#include <asm/sched_clock.h>
@@ -37,41 +36,9 @@ static void __iomem *timer_32k_base;
=20
#define OMAP16XX_TIMER_32K_SYNCHRONIZED=09=090xfffbc410
=20
-/*
- * Returns current time from boot in nsecs. It's OK for this to wrap
- * around for now, as it's just a relative time stamp.
- */
-static DEFINE_CLOCK_DATA(cd);
-
-/*
- * Constants generated by clocks_calc_mult_shift(m, s, 32768, NSEC_PER_SEC=
, 60).
- * This gives a resolution of about 30us and a wrap period of about 36hrs.
- */
-#define SC_MULT=09=094000000000u
-#define SC_SHIFT=0917
-
-static inline unsigned long long notrace _omap_32k_sched_clock(void)
-{
-=09u32 cyc =3D timer_32k_base ? __raw_readl(timer_32k_base) : 0;
-=09return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
-}
-
-#if defined(CONFIG_OMAP_32K_TIMER) && !defined(CONFIG_OMAP_MPU_TIMER)
-unsigned long long notrace sched_clock(void)
-{
-=09return _omap_32k_sched_clock();
-}
-#else
-unsigned long long notrace omap_32k_sched_clock(void)
-{
-=09return _omap_32k_sched_clock();
-}
-#endif
-
-static void notrace omap_update_sched_clock(void)
+static u32 notrace omap_32k_read_sched_clock(void)
{
-=09u32 cyc =3D timer_32k_base ? __raw_readl(timer_32k_base) : 0;
-=09update_sched_clock(&cd, cyc, (u32)~0);
+=09return timer_32k_base ? __raw_readl(timer_32k_base) : 0;
}
=20
/**
@@ -147,8 +114,7 @@ int __init omap_init_clocksource_32k(void)
=09=09=09=09=09 clocksource_mmio_readl_up))
=09=09=09printk(err, "32k_counter");
=20
-=09=09init_fixed_sched_clock(&cd, omap_update_sched_clock, 32,
-=09=09=09=09 32768, SC_MULT, SC_SHIFT);
+=09=09setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
=09}
=09return 0;
}
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/=
include/plat/common.h
index 4564cc6..44e2e33 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -41,7 +41,6 @@ extern struct sys_timer omap3_secure_timer;
extern struct sys_timer omap4_timer;
extern bool omap_32k_timer_init(void);
extern int __init omap_init_clocksource_32k(void);
-extern unsigned long long notrace omap_32k_sched_clock(void);
=20
extern void omap_reserve(void);
=20
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 69a6136..1ed8d13 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -12,7 +12,6 @@
*/
=20
#include <linux/kernel.h>
-#include <linux/sched.h>
#include <linux/timer.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
@@ -60,24 +59,10 @@ static u32 ticks_per_jiffy;
* Orion's sched_clock implementation. It has a resolution of
* at least 7.5ns (133MHz TCLK).
*/
-static DEFINE_CLOCK_DATA(cd);
=20
-unsigned long long notrace sched_clock(void)
+static u32 notrace orion_read_sched_clock(void)
{
-=09u32 cyc =3D ~readl(timer_base + TIMER0_VAL_OFF);
-=09return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-
-
-static void notrace orion_update_sched_clock(void)
-{
-=09u32 cyc =3D ~readl(timer_base + TIMER0_VAL_OFF);
-=09update_sched_clock(&cd, cyc, (u32)~0);
-}
-
-static void __init setup_sched_clock(unsigned long tclk)
-{
-=09init_sched_clock(&cd, orion_update_sched_clock, 32, tclk);
+=09return ~readl(timer_base + TIMER0_VAL_OFF);
}
=20
/*
@@ -217,7 +202,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_cl=
r_mask,
=09/*
=09 * Set scale and timer for sched_clock.
=09 */
-=09setup_sched_clock(tclk);
+=09setup_sched_clock(orion_read_sched_clock, 32, tclk);
=20
=09/*
=09 * Setup free-running clocksource timer (interrupts
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
index c833e7b..566341b 100644
--- a/arch/arm/plat-s5p/s5p-time.c
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -10,7 +10,6 @@
* published by the Free Software Foundation.
*/
=20
-#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
@@ -321,26 +320,14 @@ static void __iomem *s5p_timer_reg(void)
* this wraps around for now, since it is just a relative time
* stamp. (Inspired by U300 implementation.)
*/
-static DEFINE_CLOCK_DATA(cd);
-
-unsigned long long notrace sched_clock(void)
-{
-=09void __iomem *reg =3D s5p_timer_reg();
-
-=09if (!reg)
-=09=09return 0;
-
-=09return cyc_to_sched_clock(&cd, ~__raw_readl(reg), (u32)~0);
-}
-
-static void notrace s5p_update_sched_clock(void)
+static u32 notrace s5p_read_sched_clock(void)
{
=09void __iomem *reg =3D s5p_timer_reg();
=20
=09if (!reg)
=09=09return;
=20
-=09update_sched_clock(&cd, ~__raw_readl(reg), (u32)~0);
+=09return ~__raw_readl(reg);
}
=20
static void __init s5p_clocksource_init(void)
@@ -358,7 +345,7 @@ static void __init s5p_clocksource_init(void)
=09s5p_time_setup(timer_source.source_id, TCNT_MAX);
=09s5p_time_start(timer_source.source_id, PERIODIC);
=20
-=09init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
+=09setup_sched_clock(s5p_read_sched_clock, 32, clock_rate);
=20
=09if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer",
=09=09=09clock_rate, 250, 32, clocksource_mmio_readl_down))
diff --git a/arch/arm/plat-versatile/sched-clock.c b/arch/arm/plat-versatil=
e/sched-clock.c
index 3d6a4c2..b33b74c 100644
--- a/arch/arm/plat-versatile/sched-clock.c
+++ b/arch/arm/plat-versatile/sched-clock.c
@@ -18,41 +18,24 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 U=
SA
*/
+#include <linux/kernel.h>
#include <linux/io.h>
-#include <linux/sched.h>
=20
#include <asm/sched_clock.h>
#include <plat/sched_clock.h>
=20
-static DEFINE_CLOCK_DATA(cd);
static void __iomem *ctr;
=20
-/*
- * Constants generated by clocks_calc_mult_shift(m, s, 24MHz, NSEC_PER_SEC=
, 60).
- * This gives a resolution of about 41ns and a wrap period of about 178s.
- */
-#define SC_MULT=09=092796202667u
-#define SC_SHIFT=0926
-
-unsigned long long notrace sched_clock(void)
+static u32 notrace versatile_read_sched_clock(void)
{
-=09if (ctr) {
-=09=09u32 cyc =3D readl(ctr);
-=09=09return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0,
-=09=09=09=09=09=09SC_MULT, SC_SHIFT);
-=09} else
-=09=09return 0;
-}
+=09if (ctr)
+=09=09return readl(ctr);
=20
-static void notrace versatile_update_sched_clock(void)
-{
-=09u32 cyc =3D readl(ctr);
-=09update_sched_clock(&cd, cyc, (u32)~0);
+=09return 0;
}
=20
void __init versatile_sched_clock_init(void __iomem *reg, unsigned long ra=
te)
{
=09ctr =3D reg;
-=09init_fixed_sched_clock(&cd, versatile_update_sched_clock,
-=09=09=09 32, rate, SC_MULT, SC_SHIFT);
+=09setup_sched_clock(versatile_read_sched_clock, 32, rate);
}
--=20
1.7.0.4
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