[PATCH v7 00/14] Consolidating GIC per-cpu interrupts
marc.zyngier at arm.com
Mon Jun 13 07:21:45 EDT 2011
The current GIC per-cpu interrupts (aka PPIs) suffer from a number of
- They use a completely separate scheme to handle the interrupts,
mostly because the PPI concept doesn't really match the kernel view
of an interrupt.
- PPIs can only be used by the timer code, unless we add more low-level
- The local timer code can only be used by devices generating PPIs,
and not SPIs.
- At least one platform (msm) has started implementing its own
- Some low-level code gets duplicated, as usual...
The proposed solution is to let the GIC code expose the PPIs as
something that the kernel can manage. Instead of having a single
interrupt number shared on all cores, make the interrupt number be
different on each CPU.
This enables the use of the normal kernel API (request_irq() and
friends) and the elimination of some low level code. On the other
side, it causes quite a bit of churn in the timer code.
This patch set is based on 3.0-rc2. Tested on PB-11MP, Tegra2
(Harmony) and SMDK-V310.
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