Unnecessary cache-line flush on page table updates ?

[Catalin Marinas]

On Wed, Jul 06, 2011 at 07:08:14PM +0100, Russell King - ARM Linux wrote:
> Okay, so I can say with confidence then that how things stand in my tree,
> which limits BTC invalidation to:
> 
> 1. For kernel mappings, flush_icache_range() which must be called prior
>    to code placed in them being executed.
> 
> 2. For user mappings, __sync_icache_dcache's icache flush, which is
>    called before a non-zero user PTE is inserted.

What about:

flush_cache_user_range()
flush_ptrace_access()

They are fine as long as you haven't removed the BTC invalidation from
__cpuc_coherent_(kern|user)_range.

> The area which needs more to focus some further work is
> __sync_icache_dcache(), which is fairly over-zealous about all the
> flushing.

Another thing that could be optimised is not to clean and invalidate the
D-cache but only clean to the PoU. The only problem is that
(flush|invalidate)_kernel_vmap_area, functions that seem to used only in
a single place. The semantics in cachetlb.txt claim to be used for I/O,
which means that they are already broken since we don't handle the L2
cache.

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