[PATCH 1/2] ARM: l2x0: Errata fix for flush by Way operation can cause data corruption

[Catalin Marinas]

On 18 February 2011 12:35, Santosh Shilimkar <santosh.shilimkar at ti.com> wrote:
> PL310 implements the Clean & Invalidate by Way L2 cache maintenance
> operation (offset 0x7FC). This operation runs in background so that
> PL310 can handle normal accesses while it is in progress. Under very
> rare circumstances, due to this erratum, write data can be lost when
> PL310 treats a cacheable write transaction during a Clean & Invalidate
> by Way operation.
>
> Workaround:
> Disable Write-Back and Cache Linefill (Debug Control Register)
> Clean & Invalidate by Way (0x7FC)
> Re-enable Write-Back and Cache Linefill (Debug Control Register)
>
> This patch also removes any OMAP dependency on PL310 Errata's
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>