[PATCH v3 2/4] ARM: pxa168: Add SDHCI support

[Tanmay Upadhyay]

On Monday 19 December 2011 10:32 AM, Haojian Zhuang wrote:
> On Mon, Dec 19, 2011 at 12:55 PM, Tanmay Upadhyay
> <tanmay.upadhyay at einfochips.com>  wrote:
>>
>> On Monday 19 December 2011 10:15 AM, Haojian Zhuang wrote:
>>> On Fri, Dec 16, 2011 at 7:15 AM, Chris Ball<cjb at laptop.org>    wrote:
>>>> Hi Eric and Jason,
>>>>
>>>> On Thu, Dec 01 2011, Chris Ball wrote:
>>>>> Hi Eric, Jason,
>>>>>
>>>>> Please could you ACK this patch if you agree with it, and I'll take it
>>>>> and the rest of the series via the MMC tree?  Thanks.
>>>> Ping?
>>>>
>>>> Thanks,
>>>>
>>>> - Chris.
>>>>
>>> NACK.
>>>
>>>>>> +/* Offset defined in arch/arm/mach-mmp/include/mach/regs-apmu.h are
>>>>>> for MMP2
>>>>>> + * PXA168 has different offset */
>>>>>> +#undef APMU_SDH2
>>>>>> +#undef APMU_SDH3
>>>>>> +
>>>>>> +#define APMU_SDH2   APMU_REG(0xe0)
>>>>>> +#define APMU_SDH3   APMU_REG(0xe4)
>>>>>> +
>>> Please don't use #undef at here. If the register setting is different,
>>> I prefer to use two different clk operations.
>>>
>> Sorry I couldn't get you. Could you please elaborate? Here regs-apmu.h
>> defines clock register offsets. They are correct for MMP2, but not for
>> PXA168. So I thought to correct them in a PXA168 specific file. Could you
>> please point me a better way?
>>
>> Thanks,
>>
>> Tanmay
> APMU_PXA168_SDH2
> APMU_MMP2_SDH2
>
> I think this is better.
>

Thanks for the suggestion. This looks a better option. However, I would 
like add here that not only the register offset, but also the register 
bits are different for MMP2 & PXA168. So, the code that would control 
SD/MMC clock will be architecture specific & hence in different 
architecture specific files. Hope this solution looks good to all of you 
in that case as well.

Thanks,

Tanmay