[RFC PATCH] ARM: Fix the bug in dcache flush all API.

[Will Deacon]

On Fri, Dec 16, 2011 at 10:52:48AM +0000, R, Sricharan wrote:
>     When we work out the shift to extract the cache type bits it will go wrong
>     once we hit the 4th iteration (r10 == 6) because we'll calculate a shift of
>     10 instead of 9.
> 
> 
>         add     r2, r10, r10, lsr #1            @ work out 3x current cache
> level
>         mov     r1, r0, lsr r2                  @ extract cache type bits from
> clidr
>        
>          Here when r10=6, then r2 will be 9 , which is correct shift ?

Yes, of course, I'm on my second coffee now. I still think the line size
calculation is plain wrong though (should be 1 << (ls + 2) instead of (ls +
4)).

I'll take another look at your patch.

Will