[PATCH v4 REPOST 3/5] omap4: Unconditionally require l2x0 L2 cache controller support
tony at atomide.com
Wed Dec 14 13:14:25 EST 2011
* Dave Martin <dave.martin at linaro.org> [111214 03:08]:
> If running in the Normal World on a TrustZone-enabled SoC, Linux
> does not have complete control over the L2 cache controller
> configuration. The kernel cannot work reliably on such platforms
> without the l2x0 cache support code built in.
There are HS and GP omaps (High Security and General Purpose).
GP omaps do have full control of the L2. Also HS omaps most likely
provide control over enabling and disabling L2 depending how the
secure code is implemented.
BTW, the real problem is that because the secure code is implemented
in various ways, we don't really have any handling for it in Linux.
The SMI instruction numbers don't seem to be standardized at all,
and can mean different things on different boards, even different
board versions :(
Sounds like devicetree is the only safe way to deal with the L2
> This patch unconditionally enables l2x0 support for the OMAP4 SoCs.
> Thanks to Rob Herring for this suggestion. 
> Signed-off-by: Dave Martin <dave.martin at linaro.org>
>  http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/074495.html
> arch/arm/mach-omap2/Kconfig | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index bb1b670..94e568a 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -41,11 +41,11 @@ config ARCH_OMAP4
> bool "TI OMAP4"
> default y
> depends on ARCH_OMAP2PLUS
> + select CACHE_L2X0
> select CPU_V7
> select ARM_GIC
> select HAVE_SMP
> select LOCAL_TIMERS if SMP
> - select MIGHT_HAVE_CACHE_L2X0
> select PL310_ERRATA_588369
> select PL310_ERRATA_727915
> select ARM_ERRATA_720789
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