[PATCH v3 5/5] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4

[Pawel Moll]

On Mon, 2011-12-05 at 17:37 +0000, Dave Martin wrote:
> > I have an idea of spinning the compatible values again to get something
> > like that:
> > 
> > compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress-cortex_a5";
> > compatible = "arm,vexpress-v2p-ca9", "arm,vexpress-cortex_a9";
> > compatible = "arm,vexpress-v2p-ca15", "arm,vexpress-cortex_a15";
> 
> The trouble is, node { compatible = x } means "node is an x", not "node
> has an x".

Yes...

> So, we should be careful do document what e.g. arm,vexpress-cortex_a5
> actually means.  It doesn't mean Cortex-A5, but instead it represents
> a whole jumble of characteristics which we expect to be common to all
> vexpress-based A5 platforms.

... so I'd translate it as "is a Versatile Express platform based on
Cortex-A5 processor" and document it as such. As I said - patches
tomorrow.

> It feels that in practice arm,vexpress-cortex_a5 actually means 
> exactly the same thing as arm,vexpress-v2p-ca5s.  Are you sure these
> two are really independent?  (In other words, do we expect multiple
> different vexpress variants based on A5, and so on?)

The examples for A5 I can quota are two different SMMs I used (one on a
"small", second one on a "large" FPGA board), but they were very similar
to the A5 core tile - so similar that you could (probably) use the core
tile DTB to drive them. The A9 SMM with RS1 memory map I've mentioned is
much more interesting case - A9 platform but nothing like original A9
core tile... Also the A15 looks interesting as we will most likely get
the same tiles (as in: PCB) with different processors (as in: different
silicon). This will be fun :-)

Cheers!

Paweł