[PATCH v2 1/4] ARM: CSR: add rtc i/o bridge interface for SiRFprimaII

[Barry Song]

2011/8/24 Arnd Bergmann <arnd at arndb.de>:
> On Tuesday 23 August 2011, Barry Song wrote:
>> From: Zhiwu Song <zhiwu.song at csr.com>
>>
>> The module is a bridge between the RTC clock domain and the CPU interface
>> clock domain. ARM access the register of SYSRTC, GPSRTC and PWRC through
>> this module.
>>
>> Signed-off-by: Zhiwu Song <zhiwu.song at csr.com>
>> Signed-off-by: Barry Song <Baohua.Song at csr.com>
>> ---
>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
>
> Looks basically good now. Aside from the trivial things that Jamie
> already pointed out, there is one more that I noticed:
>
>> +
>> +void __iomem *sirfsoc_rtciobrg_base;
>> +static DEFINE_SPINLOCK(rtciobrg_lock);
>
> sirfsoc_rtciobrg_base should be static as well. No other code can
> properly access it anyway since the lock is static, too.

sirfsoc_rtciobrg_base is accessed by sleep.S too after DRAM enter
self-refresh and deepsleep is executed in cache.

        @ write SLEEPFORCE through rtc iobridge

        str     r1, [r7]
        @ wait rtc io bridge sync


>
>        Arnd