Architecture specific implementations for tickless kernel and deferrable timers

Vikram Narayanan vikram186 at
Wed Apr 20 14:15:14 EDT 2011


I am developing a BSP for a ARM Cortex-M3 (no MMU) based board. In
order to have tickless kernel and deferrable timers, what are the
architecture specific implementations. Can some one point out some
examples that already have this feature enabled and also in the kernel

And also, are clocksoure and clockevents dependent on each other? I
see in some platforms, that they have used 2 different timers for the
above. Can a same clock be used for both clocksource and clockevents?
Please throw some light on this. If it can be used so, what ties up
the clocksource and clockevent?

NOTE: As cortex-M3 doesn't have an MMU I should be using uClinux.
Since my question is very much relevant to ARM I am posting it here.


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