[PATCH] ARM: fix badly implementation of wmb

[Ming Lei]

Hi Catalin,

2011/4/17 Catalin Marinas <catalin.marinas at arm.com>:
> 3. Because Normal non-cacheable memory acceses are buffered at the L2
> cache level, we need to drain its buffer in the mb()/wmb() case, hence
> the outer_sync() call.

If you confirmed dsb plus outer_sync are needed for this case, the patch
is surely pointless. In fact, I thought dmb is enough for this case,
so introduce
the patch.  Now you have clarified it, please drop it.

>
> If you find alternatives to the points above I may agree with your patch.
>
> Please note that there have been several discussions on LKML around
> barriers for I/O vs Normal memory and the consensus was *not* to
> introduce additional barrier types since device drivers don't use them
> anyway.
>
> Can you show many situations where you would need mandatory barriers
> but not in relation to I/O?

No, thank you for the explanation, sorry for the noise.

thanks,
-- 
Ming Lei