Fri Oct 22 17:57:35 EDT 2010
The Manzano External Arch Spec says that bits 13:5 and 1:0 are read
unpredictable, not to mention the defined bits, so they must be masked.
If they are non-zero, this would cause pxa3xx_resume_after_mmu to
"restore" the modified mapping to the wrong place.
Do you agree this is a problem?
I'm using the patch below as a fix for now, but it's hard to know what
registers are available. Might be better to just mask it off the lower
bits in r1 again.
@ Let us ensure we jump to resume_after_mmu only when the mcr above
@ actually took effect. They call it the "cpwait" operation.
- mrc p15, 0, r1, c2, c0, 0 @ queue a dependency on CP15
- sub pc, r2, r1, lsr #32 @ jump to virtual addr
+ mrc p15, 0, r0, c2, c0, 0 @ queue a dependency on CP15
+ sub pc, r2, r0, lsr #32 @ jump to virtual addr
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