[PATCH] mmci: corrected calculation of clock div for ux500

[Ulf Hansson]

The Ux500 variant of this block has a different divider.
The value used right now is too big and which means a loss
in performance. This fix corrects it. Also expand the math
comments a bit so it's clear what's happening.

Signed-off-by: Ulf Hansson <ulf.hansson at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 drivers/mmc/host/mmci.c |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 7567872..0a95377 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -51,6 +51,7 @@ static unsigned int fmax =3D 515633;
  * @broken_blockend_dma: the MCI_DATABLOCKEND is broken on the hardware wh=
en
  *             using DMA.
  * @sdio: variant supports SDIO
+ * @st_clkdiv: true if using a ST-specific clock divider algorithm
  */
 struct variant_data {
        unsigned int            clkreg;
@@ -61,6 +62,7 @@ struct variant_data {
        bool                    broken_blockend;
        bool                    broken_blockend_dma;
        bool                    sdio;
+       bool                    st_clkdiv;
 };

 static struct variant_data variant_arm =3D {
@@ -86,7 +88,9 @@ static struct variant_data variant_ux500 =3D {
        .datalength_bits        =3D 24,
        .broken_blockend        =3D true,
        .sdio                   =3D true,
+       .st_clkdiv              =3D true,
 };
+
 /*
  * This must be called with host->lock held
  */
@@ -99,7 +103,22 @@ static void mmci_set_clkreg(struct mmci_host
*host, unsigned int desired)
                if (desired >=3D host->mclk) {
                        clk =3D MCI_CLK_BYPASS;
                        host->cclk =3D host->mclk;
+               } else if (variant->st_clkdiv) {
+                       /*
+                        * DB8500 TRM says f =3D mclk / (clkdiv + 2)
+                        * =3D> clkdiv =3D (mclk / f) - 2
+                        * Round the divider up so we don't exceed the max
+                        * frequency
+                        */
+                       clk =3D DIV_ROUND_UP(host->mclk, desired) - 2;
+                       if (clk >=3D 256)
+                               clk =3D 255;
+                       host->cclk =3D host->mclk / (clk + 2);
                } else {
+                       /*
+                        * PL180 TRM says f =3D mclk / (2 * (clkdiv + 1))
+                        * =3D> clkdiv =3D mclk / (2 * f) - 1
+                        */
                        clk =3D host->mclk / (2 * desired) - 1;
                        if (clk >=3D 256)
                                clk =3D 255;
--=20
1.7.3.2