[PATCH 13/20 v2] msm: 8x60: setup correct handlers for private interrupts
johlstei at codeaurora.org
Wed Oct 6 03:42:52 EDT 2010
From: Abhijeet Dharmapurikar <adharmap at codeaurora.org>
Private Peripheral interrupts could be edge triggered or level triggered
depending on the platform. Initialize handlers for these in board file.
Signed-off-by: Abhijeet Dharmapurikar <adharmap at codeaurora.org>
arch/arm/mach-msm/board-msm8x60.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index e7feb99..70087ca 100644
@@ -44,7 +44,7 @@ static void __init msm8x60_init_irq(void)
unsigned int i;
- gic_dist_init(0, MSM_QGIC_DIST_BASE, 1);
+ gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
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