[PATCH 5/5] omap4: l2x0: Enable early BRESP bit

[Måns Rullgård]

Santosh Shilimkar <santosh.shilimkar at ti.com> writes:

> The AXI protocol specifies that the write response can only
> be sent back to an AXI master when the last write data has been
> accepted. This optimization enables the PL310 to send the write
> response of certain write transactions as soon as the store buffer
> accepts the write address. This behavior is not compatible with
> the AXI protocol and is disabled by default. You enable this
> optimization by setting the Early BRESP Enable bit in the
> Auxiliary Control Register (bit [30]).

Did you measure the performance difference this makes, if any?

-- 
Måns Rullgård
mans at mansr.com