mapping uncached memory

Colin Cross ccross at
Wed Mar 17 17:26:32 EDT 2010

On Wed, Mar 17, 2010 at 1:15 AM, Russell King - ARM Linux
<linux at> wrote:
> On Wed, Mar 17, 2010 at 10:02:09AM +0200, Budhee Jamaich wrote:
>> On Wed, Mar 17, 2010 at 1:54 AM, Russell King - ARM Linux
>> <linux at> wrote:
>> from Documentation/DMA-API.txt:
>> "void *
>> dma_alloc_coherent(struct device *dev, size_t size,
>>                              dma_addr_t *dma_handle, gfp_t flag)
>> Consistent memory is memory for which a write by either the device or
>> the processor can immediately be read by the processor or device
>> without having to worry about caching effects.  (You may however need
>> to make sure to flush the processor's write buffers before telling
>> devices to read that memory.)"
>> That last sentence - what does it really say ? That I still need to
>> manually clean/invalidate the caches myself ?
> No - if it did, it would contradict the previous sentence.  What it's
> referring to is that on weakly ordered CPUs, you may need barriers.

Tegra2 needs a wmb() and an L2 cache sync on dma_alloc_coherent memory
before handing it to the device.  Currently, I am using Catalin's
patches for machine-specific wmb() implementations to do both
operations using a wmb() and keep the L2 details out of the drivers.
Is that the correct use of those patches?  Is there any other way to
handle dma_alloc_coherent memory on ARMv7?

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