[PATCH] ARM: Improve the L2 cache performance when PL310 is used
santosh.shilimkar at ti.com
Tue Mar 9 06:28:23 EST 2010
> -----Original Message-----
> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-kernel-
> bounces at lists.infradead.org] On Behalf Of Colin Tuckley
> Sent: Tuesday, March 09, 2010 4:38 PM
> To: linux-arm-kernel at lists.infradead.org
> Subject: RE: [PATCH] ARM: Improve the L2 cache performance when PL310 is used
> > -----Original Message-----
> > From: Catalin Marinas
> > But do they use an L220? Or they don't use anything?
> The A8 has it's own L2 cache design, the chip used on the PBA8 has a bit tacked on that makes it look
> a bit like a 220. I'm also told that it's possible to implement an A8 without a level two cache.
> I think this is a case of reading the docs or maybe raising an Arm-support ticket.
Just as an example,
Both OMAP3 and OMAP4 are based on ARMv7. OMAP3 there is Cortex-A8 with internal
L2 cache where as OMAP4 is Cortex-A9 with Pl310 as external L2. So below
approach from Catalin should work at least for v7 based OMAPs for sure.
+ depends on CACHE_L2X0
+ default y if CPU_V7
+ This option enables support for the PL310 cache controller.
OMAP3 -- "CACHE_PL310" won't be enabled because "CACHE_L2X0" isn't enabled.
OMAP4 -- PL310 is enabled because "CACHE_L2X0" is enabled
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