[patch 0/2] ARM: Disable outer cache before kexec call
santosh.shilimkar at ti.com
Thu Jul 1 12:38:37 EDT 2010
> -----Original Message-----
> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-
> kernel-bounces at lists.infradead.org] On Behalf Of Thomas Gleixner
> Sent: Thursday, July 01, 2010 9:59 PM
> To: Catalin Marinas
> Cc: LAK
> Subject: Re: [patch 0/2] ARM: Disable outer cache before kexec call
> On Thu, 1 Jul 2010, Catalin Marinas wrote:
> > On Thu, 2010-07-01 at 17:05 +0100, Thomas Gleixner wrote:
> > > The following patch series addresses the problem, that the kexec code
> > > does not disable the outer cache before disabling the inner cache and
> > > jumping into the new kernel. This results in random crashes of the new
> > > kernel.
> > We may need other ways to work around this problem. There are platforms
> > like OMAP3 (I think) where the L2 cache cannot be disabled as Linux is
> > running in non-secure (normal) mode.
> But it can disable the inner caches? That's weird.
If the C bit is disabled then it is as good as L1 and L2 are disabled.
> > Cannot some extra cache flushing work around this problem?
> We tried to keep the L2 on and just doing the l2x0_inv_all() call and
> it hangs.
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