[RFC 05/18] arm: msm: implement ioremap_strongly_ordered
lbassel at quicinc.com
Thu Jan 28 18:04:49 EST 2010
On Mon, Jan 11, 2010 at 03:37:20PM -0800, Russell King - ARM Linux wrote:
> On Mon, Jan 11, 2010 at 02:47:24PM -0800, Daniel Walker wrote:
> > From: Larry Bassel <lbassel at quicinc.com>
> > Both the clean and invalidate functionality needed
> > for the video encoder and 7x27 barrier code
> > need to have a strongly ordered mapping set up
> > so that one may perform a write to strongly ordered
> > memory. The generic ARM code does not provide this.
> > The generic ARM code does provide MT_DEVICE, which starts
> > as strongly ordered, but the code later turns the buffered flag
> > on for ARMv6 in order to make the device shared. This is not
> > suitable for my purpose, so this patch adds code for a
> > MT_DEVICE_STRONGLY_ORDERED mapping type.
> This doesn't really describe what "my purpose" is; the patch description
> is too vague to ascertain why this is required.
Hopefully this is a better description of the patch:
Some Qualcomm SOCs (such as the MSM7x27) require a write to
strongly ordered memory in order to fully flush the AXI bus.
Although the generic ARM code provides MT_DEVICE, which starts
as strongly ordered, it later turns on the buffered flag to
make this memory shared.
Add an additional mapping type MT_DEVICE_STRONGLY_ORDERED which
will stay in strongly ordered mode and allow proper
implementation of cache and invalidate operations on these
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