[RFC PATCH 05/12] arm: mm: retry on QSD icache parity errors

[Pavel Machek]

Hi!

> Parity errors in the icache on QSD can be worked around either by
> retrying the access, or invalidating the icache. The whole icache
> must be invalidated since the data abort is imprecise (the faulting
> address is not known).
> 
> Signed-off-by: Steve Muckle <smuckle at quicinc.com>
> Signed-off-by: Daniel Walker <dwalker at codeaurora.org>


> @@ -442,6 +443,39 @@ do_bad(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
>  	return 1;
>  }
>  
> +static int
> +do_imprecise_ext(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
> +{
> +#ifdef CONFIG_ARCH_MSM_SCORPION
> +	unsigned int regval;
> +	static unsigned char flush_toggle;
> +
> +	asm("mrc p15, 0, %0, c5, c1, 0\n" /* read adfsr for fault status */
> +	    : "=r" (regval));
> +	if (regval == 0x2) {
> +		/* Fault was caused by icache parity error. Alternate
> +		 * simply retrying the access and flushing the icache. */
> +		flush_toggle ^= 1;
> +		if (flush_toggle)
> +			asm("mcr p15, 0, %0, c7, c5, 0\n"
> +			    :
> +			    : "r" (regval)); /* input value is ignored */
> +		/* Clear fault in EFSR. */
> +		asm("mcr p15, 7, %0, c15, c0, 1\n"
> +		    :
> +		    : "r" (regval));
> +		/* Clear fault in ADFSR. */
> +		regval = 0;
> +		asm("mcr p15, 0, %0, c5, c1, 0\n"
> +		    :
> +		    : "r" (regval));
> +		return 0;
> +	}
> +#endif

Tell the user or at least keep the count, so cache going bad can be
recognized?

Also you probably need asm volatile, and probably do not need those
\n-s.

									Pavel
-- 
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