[PATCH 3/5] gic: Add set_type callback

[adharmap at codeaurora.org]

From: Abhijeet Dharmapurikar <adharmap at quicinc.com>

Add gic_set_type callback to set an irq as level or edge triggered type

Signed-off-by: Abhijeet Dharmapurikar <adharmap at quicinc.com>
---
 arch/arm/common/gic.c |   43 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 43 insertions(+), 0 deletions(-)

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 00172c4..709cf53 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -165,6 +165,48 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 	chip->unmask(irq);
 }
 
+static int gic_set_type(unsigned int irq, unsigned int flow_type)
+{
+	unsigned int register_index;
+	unsigned int bit_index;
+	unsigned int reg_value;
+
+	if (irq > 1020)
+		return -1;
+
+	/*
+	* Two bits each, calc the register and bit, 16 per 32 bit register
+	* accessible long word only
+	* But the field is NxN 1xN and rising/falling
+	*/
+	register_index = (irq/16)<<2;
+	bit_index = (irq & 0xF)<<1;
+
+	spin_lock(&irq_controller_lock);
+	reg_value = readl(gic_dist_base(irq) + GIC_DIST_CONFIG +
+						register_index);
+	/*
+	* keep the nxn and 1xn , mask the edge level
+	* Edge is 1, level 0
+	*/
+	reg_value = (reg_value & ~(2<<bit_index));
+	if (flow_type & (IRQ_TYPE_EDGE_RISING|IRQ_TYPE_EDGE_FALLING)) {
+		reg_value |= (2<<bit_index);
+		writel(reg_value, gic_dist_base(irq) + GIC_DIST_CONFIG
+							+ register_index);
+		__set_irq_handler_unlocked(irq, handle_edge_irq);
+	}
+
+	if (flow_type & (IRQ_TYPE_LEVEL_HIGH|IRQ_TYPE_LEVEL_LOW)) {
+		writel(reg_value, gic_dist_base(irq) + GIC_DIST_CONFIG
+							+ register_index);
+		__set_irq_handler_unlocked(irq, handle_level_irq);
+	}
+
+	spin_unlock(&irq_controller_lock);
+	return 0;
+}
+
 static struct irq_chip gic_chip = {
 	.name		= "GIC",
 	.ack		= gic_ack_irq,
@@ -174,6 +216,7 @@ static struct irq_chip gic_chip = {
 #ifdef CONFIG_SMP
 	.set_affinity	= gic_set_cpu,
 #endif
+	.set_type	= gic_set_type,
 };
 
 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
-- 
1.5.6.3