[PATCH 1/4] ARM: Change the mandatory barriers implementation

[Russell King - ARM Linux]

On Tue, Feb 23, 2010 at 11:01:05AM +0000, Catalin Marinas wrote:
> The mandatory barriers (mb, rmb, wmb) are used even on uniprocessor
> systems for things like ordering Normal Non-cacheable memory accesses
> with DMA transfer (via Device memory writes). The current implementation
> uses dmb() for mb() and friends but this is not sufficient. The DMB only
> ensures the ordering of accesses with regards to a single observer
> accessing the same memory.

Erm, I also don't think your statement here is right.  DMB is defined in
the ARM ARM to be by default a full-system, read/write memory barrier.
It has this property:

  If the required shareability is Full system then the operation applies
  to all observers within the system.
...
  Any observer with the same required shareability domain as Pe observes
  all members of Group A before it observes any member of Group B to the
  extent that those group members are required to be observed, as
  determined by the shareability and cacheability of the memory locations
  accessed by the group members.  Where members of Group A and Group B
  access the same memory-mapped peripheral, all members of Group A will
  be visible at the memory-mapped peripheral before any members of Group
  B are visible at that peripheral.

This most definitely is not "single observer" - it's all observers within
the same "shareability domain".  That may encompass all CPUs and not
devices and DMA agents.

I'd go further - in the case of:

	write to non-cacheable memory
	dmb();
	write to peripheral

then, because the dmb() is a full system dmb, all observers within the
system should see the write to non-cacheable memory before the write to
peripheral.

Either that or the ARM ARM is unclear/wrong about what "all observers"
means.