[PATCHv2 04/11] mxc: changes to common plat-mxc code to add support for i.MX5
Eric Miao
eric.y.miao at gmail.com
Wed Feb 3 01:43:33 EST 2010
On Tue, Feb 2, 2010 at 9:16 PM, Amit Kucheria
<amit.kucheria at canonical.com> wrote:
> Changes separted to help in the review process
>
> Signed-off-by: Amit Kucheria <amit.kucheria at canonical.com>
> ---
> arch/arm/plat-mxc/include/mach/common.h | 4 +++
> arch/arm/plat-mxc/include/mach/debug-macro.S | 9 +++++++
> arch/arm/plat-mxc/include/mach/entry-macro.S | 34 +++++++++++++++++++++++++-
> arch/arm/plat-mxc/include/mach/hardware.h | 4 +++
> arch/arm/plat-mxc/include/mach/irqs.h | 9 ++++++-
> arch/arm/plat-mxc/include/mach/memory.h | 3 ++
> arch/arm/plat-mxc/include/mach/mxc.h | 13 ++++++++++
> arch/arm/plat-mxc/include/mach/timex.h | 2 +
> arch/arm/plat-mxc/time.c | 6 ++--
> 9 files changed, 79 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
> index 286cb9b..5250a3f 100644
> --- a/arch/arm/plat-mxc/include/mach/common.h
> +++ b/arch/arm/plat-mxc/include/mach/common.h
> @@ -20,8 +20,10 @@ extern void mx25_map_io(void);
> extern void mx27_map_io(void);
> extern void mx31_map_io(void);
> extern void mx35_map_io(void);
> +extern void mx51_map_io(void);
> extern void mxc91231_map_io(void);
> extern void mxc_init_irq(void __iomem *);
> +extern void tzic_init_irq(void __iomem *);
> extern void mx1_init_irq(void);
> extern void mx21_init_irq(void);
> extern void mx25_init_irq(void);
> @@ -36,6 +38,8 @@ extern int mx25_clocks_init(unsigned long fref);
> extern int mx27_clocks_init(unsigned long fref);
> extern int mx31_clocks_init(unsigned long fref);
> extern int mx35_clocks_init(void);
> +extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
> + unsigned long ckih1, unsigned long ckih2);
> extern int mxc91231_clocks_init(unsigned long fref);
> extern int mxc_register_gpios(void);
> extern int mxc_register_device(struct platform_device *pdev, void *data);
> diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
> index 15b2b14..9fe7300 100644
> --- a/arch/arm/plat-mxc/include/mach/debug-macro.S
> +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
> @@ -44,6 +44,15 @@
> #define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
> #endif
>
> +#ifdef CONFIG_ARCH_MX5
> +#ifdef UART_PADDR
> +#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
> +#endif
> +#include <mach/mx51.h>
> +#define UART_PADDR UART1_BASE_ADDR
> +#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
> +#endif
> +
> #ifdef CONFIG_ARCH_MXC91231
> #ifdef UART_PADDR
> #error "CONFIG_DEBUG_LL is incompatible with multiple archs"
> diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
> index 7cf290e..aeb0869 100644
> --- a/arch/arm/plat-mxc/include/mach/entry-macro.S
> +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
> @@ -1,6 +1,6 @@
> /*
> * Copyright (C) 2007 Lennert Buytenhek <buytenh at wantstofly.org>
> - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
> + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
> */
>
> /*
> @@ -18,11 +18,16 @@
> .endm
>
> .macro get_irqnr_preamble, base, tmp
> +#ifndef CONFIG_MXC_TZIC
> ldr \base, =avic_base
> ldr \base, [\base]
> #ifdef CONFIG_MXC_IRQ_PRIOR
> ldr r4, [\base, #AVIC_NIMASK]
> #endif
> +#elif defined CONFIG_MXC_TZIC
> + ldr \base, =tzic_base
> + ldr \base, [\base]
> +#endif /* CONFIG_MXC_TZIC */
Mmm.... this should be something that we really need to get rid of, it just
makes a single kernel for both TZIC and AVIC together impossible, if that's
so designed by HW, I'm thinking about keeping this into plat-mxc/ is a good
way to go ...
Sascha, you have any better idea? Provided the other file debug-macro.S in
the same directory already seems to break the support for multiple arches?
> .endm
>
> .macro arch_ret_to_user, tmp1, tmp2
> @@ -32,6 +37,7 @@
> @ and returns its number in irqnr
> @ and returns if an interrupt occured in irqstat
> .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
> +#ifndef CONFIG_MXC_TZIC
> @ Load offset & priority of the highest priority
> @ interrupt pending from AVIC_NIVECSR
> ldr \irqstat, [\base, #0x40]
> @@ -45,6 +51,32 @@
> strne \tmp, [\base, #AVIC_NIMASK]
> streq r4, [\base, #AVIC_NIMASK]
> #endif
> +#elif defined CONFIG_MXC_TZIC
> + @ Load offset & priority of the highest priority
> + @ interrupt pending.
> + @ 0xD80 is HIPND0 register
> + mov \irqnr, #0
> + mov \irqstat, #0x0D80
> +1000:
> + ldr \tmp, [\irqstat, \base]
> + cmp \tmp, #0
> + bne 1001f
> + addeq \irqnr, \irqnr, #32
> + addeq \irqstat, \irqstat, #4
> + cmp \irqnr, #128
> + blo 1000b
> + b 2001f
> +1001: mov \irqstat, #1
> +1002: tst \tmp, \irqstat
> + bne 2002f
> + movs \tmp, \tmp, lsr #1
> + addne \irqnr, \irqnr, #1
> + bne 1002b
> +2001:
> + mov \irqnr, #0
> +2002:
> + movs \irqnr, \irqnr
> +#endif
> .endm
>
> @ irq priority table (not used)
> diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
> index 78db754..55ebe88 100644
> --- a/arch/arm/plat-mxc/include/mach/hardware.h
> +++ b/arch/arm/plat-mxc/include/mach/hardware.h
> @@ -22,6 +22,10 @@
>
> #include <asm/sizes.h>
>
> +#ifdef CONFIG_ARCH_MX5
> +#include <mach/mx51.h>
> +#endif
> +
> #ifdef CONFIG_ARCH_MX3
> #include <mach/mx3x.h>
> #include <mach/mx31.h>
> diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
> index ead9d59..24c066e 100644
> --- a/arch/arm/plat-mxc/include/mach/irqs.h
> +++ b/arch/arm/plat-mxc/include/mach/irqs.h
> @@ -12,9 +12,13 @@
> #define __ASM_ARCH_MXC_IRQS_H__
>
> /*
> - * So far all i.MX SoCs have 64 internal interrupts
> + * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
> */
> +#ifdef CONFIG_MXC_TZIC
> +#define MXC_INTERNAL_IRQS 128
> +#else
> #define MXC_INTERNAL_IRQS 64
> +#endif
>
> #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
>
> @@ -26,6 +30,8 @@
> #define MXC_GPIO_IRQS (32 * 3)
> #elif defined CONFIG_ARCH_MX25
> #define MXC_GPIO_IRQS (32 * 4)
> +#elif defined CONFIG_ARCH_MX5
> +#define MXC_GPIO_IRQS (32 * 4)
> #elif defined CONFIG_ARCH_MXC91231
> #define MXC_GPIO_IRQS (32 * 4)
> #endif
> @@ -46,6 +52,7 @@
> #else
> #define MX3_IPU_IRQS 0
> #endif
> +/* REVISIT: Add IPU irqs on IMX51 */
>
> #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
>
> diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
> index d3afafd..e46626e 100644
> --- a/arch/arm/plat-mxc/include/mach/memory.h
> +++ b/arch/arm/plat-mxc/include/mach/memory.h
> @@ -27,6 +27,9 @@
> #elif defined CONFIG_ARCH_MXC91231
> #define PHYS_OFFSET UL(0x90000000)
> #endif
> +#ifdef CONFIG_ARCH_MX5
> +#define PHYS_OFFSET UL(0x90000000)
> +#endif
>
> #if defined(CONFIG_MX1_VIDEO)
> /*
> diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
> index 5199053..555e5f8 100644
> --- a/arch/arm/plat-mxc/include/mach/mxc.h
> +++ b/arch/arm/plat-mxc/include/mach/mxc.h
> @@ -30,6 +30,7 @@
> #define MXC_CPU_MX27 27
> #define MXC_CPU_MX31 31
> #define MXC_CPU_MX35 35
> +#define MXC_CPU_MX51 51
> #define MXC_CPU_MXC91231 91231
>
> #ifndef __ASSEMBLY__
> @@ -108,6 +109,18 @@ extern unsigned int __mxc_cpu_type;
> # define cpu_is_mx35() (0)
> #endif
>
> +#ifdef CONFIG_ARCH_MX5
> +# ifdef mxc_cpu_type
> +# undef mxc_cpu_type
> +# define mxc_cpu_type __mxc_cpu_type
> +# else
> +# define mxc_cpu_type MXC_CPU_MX51
> +# endif
> +# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
> +#else
> +# define cpu_is_mx51() (0)
> +#endif
> +
> #ifdef CONFIG_ARCH_MXC91231
> # ifdef mxc_cpu_type
> # undef mxc_cpu_type
> diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
> index 527a6c2..024416e 100644
> --- a/arch/arm/plat-mxc/include/mach/timex.h
> +++ b/arch/arm/plat-mxc/include/mach/timex.h
> @@ -28,6 +28,8 @@
> #define CLOCK_TICK_RATE 16625000
> #elif defined CONFIG_ARCH_MX25
> #define CLOCK_TICK_RATE 16000000
> +#elif defined CONFIG_ARCH_MX5
> +#define CLOCK_TICK_RATE 8000000
> #elif defined CONFIG_ARCH_MXC91231
> #define CLOCK_TICK_RATE 13000000
> #endif
> diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
> index 7d6499e..2ba8b29 100644
> --- a/arch/arm/plat-mxc/time.c
> +++ b/arch/arm/plat-mxc/time.c
> @@ -32,7 +32,7 @@
>
> /* defines common for all i.MX */
> #define MXC_TCTL 0x00
> -#define MXC_TCTL_TEN (1 << 0)
> +#define MXC_TCTL_TEN (1 << 0) /* Enable module */
> #define MXC_TPRER 0x04
>
> /* MX1, MX21, MX27 */
> @@ -48,7 +48,7 @@
> #define MX2_TSTAT_COMP (1 << 0)
>
> /* MX31, MX35, MX25, MXC91231 */
> -#define MX3_TCTL_WAITEN (1 << 3)
> +#define MX3_TCTL_WAITEN (1 << 3) /* Wait enable mode */
> #define MX3_TCTL_CLK_IPG (1 << 6)
> #define MX3_TCTL_FRR (1 << 9)
> #define MX3_IR 0x0c
> @@ -58,7 +58,7 @@
> #define MX3_TCMP 0x10
>
> #define timer_is_v1() (cpu_is_mx1() || cpu_is_mx27())
> -#define timer_is_v2() (cpu_is_mx3() || cpu_is_mx25())
> +#define timer_is_v2() (cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51())
>
> static struct clock_event_device clockevent_mxc;
> static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
> --
> 1.6.3.3
>
>
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