[PATCH v2] [ARM] gic: Unmask private interrupts on all cores during IRQ enable
scaudle at codeaurora.org
Thu Dec 16 09:54:23 EST 2010
On 12/09/2010 11:24 AM, Stephen Caudle wrote:
>> It is also unreasonable to have one core enabling the PPI on other
>> cores where the hardware behind the interrupt may not have been
>> initialized yet. If it is a private interrupt for a private peripheral,
>> then only the associated CPU should be enabling that interrupt.
>> I guess this is something which genirq can't cope with, in which case
>> either genirq needs to be modified to cope with private CPU interrupts,
>> which are controlled individually by their associated CPU, or we need a
>> private interface to support this.
> I see your point. Our immediate need for this is to support a
> performance monitor interrupt that happens to be a PPI. It is used by
> perf events (and subsequently, oprofile).
> Since PPIs are so machine-specific, I started looking into patching
> perf_events.c by adding a machine specific function to handle the PMU
> IRQ request. For mach-msm, we would call request_irq like normal, but
> also unmask the performance monitor interrupt on the other cores. The
> downside to this is that a machine specific implementation would be
> needed anytime a PPI is requested, not just in perf_events.c.
> Then, I saw Thomas' email regarding our local timer PPI:
> Russell, before I submit another patch, I would like to know if you
> prefer a more generic approach like Thomas suggests, or a
> machine-specific approach like I have described?
Russell, what are your thoughts on this?
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
More information about the linux-arm-kernel