amba clcd clock/timing check mismatch

[Kevin Wells]

>> >From the include/linux/amba/clcd.h file, in the clcdfb_check() function...
>>
>> #define CHECK(e,l,h) (var->e < l || var->e > h)
>>       if (CHECK(right_margin, (5+1), 256) ||  /* back porch */
>>           CHECK(left_margin, (5+1), 256) ||   /* front porch */
>>           CHECK(hsync_len, (5+1), 256) ||
>>           var->xres > 4096 ||
>>
>> These 4 checks don't match the actual values that can be
>> generated by the CLCD controller. The minimum values for left
>> and right horizontal porch and HSYNC width can go down to
>> 1 clock.
>
> Not quite - these restrictions deal with the restrictions for DMA
> timing for STN panels as specified in the CLCD documentation -
> clcdfb_check doesn't deal with the differences between STN and
> active panels.
>
> So it's not as simple as just reducing these down to allowing 1 clock
> - that'd break STN panels.
>

I didn't realize those limits were for STN. With TFT HS width at 5 clocks,
the check fails on my board, I'll have to create a variant of this function
on the phy3250 platform.

>> The maximum x resolution for the pl11x devices is 1024 pixels.
>
> Yes, you seem to be right here.
>

It's probably not worth a patch unless something changes elsewhere
in clcd.h.