No subject

"Configuration cycles are non-burst and restricted to a single 32-bit
word cycle"
...
"The user should designate the memory region containing the OCCDR as
non-cacheable and non-bufferable from the Intel XScale=AE core.  This
guarantees that all load/stores to the OCCDR is only of DWORD
quantities. In event the user inadvertently issues a read to the OCCDR
that crosses a DWORD address boundary, the ATU target aborts the
transaction. All writes is terminated with a Single-Phase-Disconnect
and only bytes 3:0 is relevant."

I believe sub-dword access were once verified to work, but I no longer
have access to those test results.  However, the following at least
boots on my iop13xx, so I'll look into this a bit more.

Thanks,
Dan

diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 4873f26..1b6a65a 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -190,7 +190,7 @@ static u32 iop13xx_atux_cfg_address(struct pci_bus
*bus, int devfn, int where)
        else
                addr =3D bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;

-       addr |=3D PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
+       addr |=3D PCI_FUNC(devfn) << 8 | (where & 0xff);
        addr |=3D ((where & 0xf00) >> 8) << 24; /* upper register number */

        return addr;
@@ -264,7 +264,7 @@ static u32 iop13xx_atux_read(unsigned long addr)
 {
        u32 val;

-       __asm__ __volatile__(
+       asm volatile(
                "str    %1, [%2]\n\t"
                "ldr    %0, [%3]\n\t"
                "mov    %0, %0\n\t"
@@ -281,7 +281,7 @@ static int
 iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int wher=
e,
                int size, u32 *value)
 {
-       unsigned long addr =3D iop13xx_atux_cfg_address(bus, devfn, where);
+       unsigned long addr =3D iop13xx_atux_cfg_address(bus, devfn, where &=
 ~3);
        u32 val =3D iop13xx_atux_read(addr) >> ((where & 3) * 8);

        if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
@@ -300,25 +300,14 @@ iop13xx_atux_write_config(struct pci_bus *bus,
unsigned int devfn, int where,
                int size, u32 value)
 {
        unsigned long addr =3D iop13xx_atux_cfg_address(bus, devfn, where);
-       u32 val;
-
-       if (size !=3D 4) {
-               val =3D iop13xx_atux_read(addr);
-               if (!iop13xx_atux_pci_status(1) =3D=3D 0)
-                       return PCIBIOS_SUCCESSFUL;
-
-               where =3D (where & 3) * 8;

-               if (size =3D=3D 1)
-                       val &=3D ~(0xff << where);
-               else
-                       val &=3D ~(0xffff << where);
-
-               __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
-       } else {
-               __raw_writel(addr, IOP13XX_ATUX_OCCAR);
+       __raw_writel(addr, IOP13XX_ATUX_OCCAR);
+       if (size =3D=3D 1)
+               __raw_writeb(value, IOP13XX_ATUX_OCCDR);
+       else if (size =3D=3D 2)
+               __raw_writew(value, IOP13XX_ATUX_OCCDR);
+       else
                __raw_writel(value, IOP13XX_ATUX_OCCDR);
-       }

        return PCIBIOS_SUCCESSFUL;
 }