Why flush_cache_all() not including flushing L2 cache if the system has L2 cache?

[Peter Chen]

Eric Miao wrote:
> On Mon, Nov 2, 2009 at 10:32 AM, Peter Chen <hzpeterchen at gmail.com> wrote:
>> Dear list,
>>
>> I met a problem if the address is first used by cachable, then uncachable.
>> After that, the address will be filled with cachable value
>> after that L2 cache line is evicted.
>>
> 
> L2 cache is usually physically tagged, and from the CPU POV, it's
> consistent once the L1 is flushed.
My SoC platform is arm11, and L2 is PIPT. what do you mean " from the 
CPU POV, it's consistent once the L1 is flushed"?
> 
> If you have problems with L2 not being flushed, it's most likely a
> device issue, which means you probably need the dma_ API.
> 
I know it can be fixed by using dma_ API for alloc uncachable address.
But If someone uses uncachable memory address before flush it, it is 
problem. Since L1 should be flushed at code, why L2 not?

Thank you!
-- 
Best regards,
Peter Chen