shared memory problem on ARM v5TE using threads

[Russell King - ARM Linux]

On Sun, Dec 13, 2009 at 01:48:48PM +0200, Ronen Shitrit wrote:
> Another idea is to change the shared mapping handling, in case of vivt with pipt L2, so it won't remap the shared area as non-cacheable:
> - make_coherent won't use adjust_pte and leave only the regular flush.
> - Flush L1 for all context switches, also for the case that the new process is using same mm (thread context switch).

That doesn't work.

Well, with a VIVT L1, we flush the L1 on all MM switches anyway.
Flushing it on any thread switch is not going to help that much.

The problem with shared mmaps is that if you have multiple within the
same thread, it is required that they are _all_ coherent with respect
to each other, whether or not a context switch has occurred.

I believe there are databases (eg, db4) which are non-threaded, makes
use of multiple shared mappings and requires that it works, otherwise
the database becomes corrupted.

Unfortunately, this means your suggestion is not a solution at all.

I'm afraid to say that the only solution I can see to this problem is to
disable the L2 cache outright on these CPUs - the choice seems to be
between correct system behaviour and lower performance, or performance
but buggy system behaviour in certain cases leading to data corruption.

I know which I'd prefer.