[PATCH 1/3] dt-bindings: pwm: amlogic: Add core clock for T7
sashiko-bot at kernel.org
sashiko-bot at kernel.org
Thu Sep 24 08:25:13 PDT 2026
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dt-bindings: pwm: amlogic: ABI break for amlogic,t7-pwm
--
commit ea055f0ab3ecf76a41b2a2cf99ee615eac00cdc9
Author: Ronald Claveau <linux-kernel-dev at aliel.fr>
dt-bindings: pwm: amlogic: Add core clock for T7
This commit adds a third core clock for the amlogic,t7-pwm compatible
binding and requires clock-names for this SoC. Other compatibles are left
unchanged, and an example is added for T7 usage.
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
> index c337d85da40f1..9212a40d9fe48 100644
> --- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
> +++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
[ ... ]
> @@ -135,17 +135,38 @@ allOf:
> properties:
> compatible:
> contains:
> - enum:
> - - amlogic,meson-s4-pwm
> + const: amlogic,t7-pwm
> then:
> properties:
> clocks:
> items:
> - description: input clock of PWM channel A
> - description: input clock of PWM channel B
> - clock-names: false
> + - description: gate clock for the PWM controller
> + clock-names:
> + items:
> + - const: clk_a
> + - const: clk_b
> + - const: core
> required:
> - clocks
> + - clock-names
[Severity: Medium]
Does this introduce a schema validation regression for older device trees?
By defining exactly three items in the clocks list and strictly requiring
the clock-names property, older device trees that only provide two clocks
and omit clock-names will fail validation. Device tree schemas typically
must maintain backward compatibility with older or out-of-tree DTBs.
Should the schema specify a minimum item count of 2 for clocks and only
conditionally require clock-names based on the number of clocks provided
to avoid an ABI break?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260924-add-t7-sys-pwm-clk-v1-0-05b91e87f0a9@aliel.fr?part=1
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