[PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock controller node

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu at amlogic.com>

Add the peripherals clock controller node for A4 SoC family.

Signed-off-by: Chuan Liu <chuan.liu at amlogic.com>
---
 arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 39 +++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
index aca81e658654..3404358aff58 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/pinctrl/amlogic,pinctrl.h>
 #include <dt-bindings/clock/amlogic,a4-pll-clkc.h>
 #include <dt-bindings/clock/amlogic,a4-scmi-clkc.h>
+#include <dt-bindings/clock/amlogic,a4-peripherals-clkc.h>
 
 / {
 	cpus {
@@ -83,6 +84,44 @@ scmi_clk: protocol at 14 {
 };
 
 &apb {
+	clkc_periphs: clock-controller at 0 {
+		compatible = "amlogic,a4-peripherals-clkc";
+		reg = <0x0 0x0 0x0 0x20c>;
+		#clock-cells = <1>;
+		clocks = <&xtal>,
+			 <&scmi_clk CLKID_OSC>,
+			 <&scmi_clk CLKID_FIXED_PLL>,
+			 <&scmi_clk CLKID_FCLK_DIV2>,
+			 <&scmi_clk CLKID_FCLK_DIV2P5>,
+			 <&scmi_clk CLKID_FCLK_DIV3>,
+			 <&scmi_clk CLKID_FCLK_DIV4>,
+			 <&scmi_clk CLKID_FCLK_DIV5>,
+			 <&scmi_clk CLKID_FCLK_DIV7>,
+			 <&clkc_pll CLKID_GP0_PLL>,
+			 <&scmi_clk CLKID_GP1_PLL>,
+			 <&clkc_pll CLKID_HIFI_PLL>,
+			 <&scmi_clk CLKID_SYS_CLK>,
+			 <&scmi_clk CLKID_AXI_CLK>,
+			 <&scmi_clk CLKID_SYS_PLL_DIV16>,
+			 <&scmi_clk CLKID_CPU_CLK_DIV16>;
+		clock-names = "xtal",
+			      "oscin",
+			      "fix",
+			      "fdiv2",
+			      "fdiv2p5",
+			      "fdiv3",
+			      "fdiv4",
+			      "fdiv5",
+			      "fdiv7",
+			      "gp0",
+			      "gp1",
+			      "hifi",
+			      "sysclk",s
+			      "axiclk",
+			      "sysplldiv16",
+			      "cpudiv16";
+	};
+
 	reset: reset-controller at 2000 {
 		compatible = "amlogic,a4-reset",
 			     "amlogic,meson-s4-reset";

-- 
2.42.0