[PATCH v2 4/4] pwm: meson: make full use of common clock framework

[Heiner Kallweit]

On 11.04.2023 21:48, Martin Blumenstingl wrote:
> On Tue, Apr 11, 2023 at 9:26 PM Heiner Kallweit <hkallweit1 at gmail.com> wrote:
> [...]
>> +               init.name = name;
>> +               init.ops = &clk_gate_ops;
>> +               init.flags = CLK_SET_RATE_PARENT;
> As much as I don't want it: I think we need CLK_IGNORE_UNUSED here as well :-(
> On GXBB, GXL and GXM SoCs the board design typically uses PWM
> regulators (like the boards using 32-bit SoCs as well as newer boards
> using G12A or later SoCs).
> This means: if we enable that PWM controller and one of the channels
> is firmware managed and the other isn't then we can end up disabling
> the clock - taking away VCCK (which supplies the CPU) or VDDEE (which
> supplies GPU and various other components).

I see your point, good to know. Eventually it may be an option to
mark such firmware-managed pwm channels in DT.
I'll wait for potential additional feedback until tomorrow, then I'll
submit a version incl. the two small changes to address your remarks.

> I'd be happy if there are other suggestions around this though.
> 
> 
> Best regards,
> Martin