[PATCH v2 4/4] pwm: meson: make full use of common clock framework

Martin Blumenstingl martin.blumenstingl at googlemail.com
Tue Apr 11 12:48:46 PDT 2023


On Tue, Apr 11, 2023 at 9:26 PM Heiner Kallweit <hkallweit1 at gmail.com> wrote:
[...]
> +               init.name = name;
> +               init.ops = &clk_gate_ops;
> +               init.flags = CLK_SET_RATE_PARENT;
As much as I don't want it: I think we need CLK_IGNORE_UNUSED here as well :-(
On GXBB, GXL and GXM SoCs the board design typically uses PWM
regulators (like the boards using 32-bit SoCs as well as newer boards
using G12A or later SoCs).
This means: if we enable that PWM controller and one of the channels
is firmware managed and the other isn't then we can end up disabling
the clock - taking away VCCK (which supplies the CPU) or VDDEE (which
supplies GPU and various other components).
I'd be happy if there are other suggestions around this though.


Best regards,
Martin



More information about the linux-amlogic mailing list