[PATCH V2 1/2] tty: serial: meson: Add a 12MHz internal clock rate to calculate baud rate in order to meet the baud rate requirements of special BT modules

[Yu Tu]

Hi Neil,

On 2022/4/21 16:46, Neil Armstrong wrote:
> [ EXTERNAL EMAIL ]
> 
> Hi Andy,
> 
> On 18/04/2022 14:09, Andy Shevchenko wrote:
>> On Mon, Apr 18, 2022 at 8:50 AM Yu Tu <yu.tu at amlogic.com> wrote:
>>>
>>> A /2 divider over XTAL was introduced since G12A, and is preferred
>>> to be used over the still present /3 divider since it provides much
>>> closer frequencies vs the request baudrate.Especially the BT module
>>
>> 'e. E' (mind the space)
>>
>>> uses 3Mhz baud rate. 8Mhz calculations can lead to baud rate bias,
>>> causing some problems.
>>
>> ...
>>
>>> +struct meson_uart_data {
>>> +       bool has_xtal_div2;
>>
>> I would prefer to see this as an unsigned int and with a less
>> particular name, e.g. xtal_div would suffice.
>>
>>> +};
>>
>> ...
>>
>>> +               unsigned int xtal_div = 3;
>>
>>> +               if (private_data && private_data->has_xtal_div2) {
>>> +                       xtal_div = 2;
>>
>> Better to define privata data always
> 
> While I'm in favor of defining private data, here 3 and 2 are actually 
> the values
> 2 and 3 used to divide.
> 
> The code is easy to read and we quickly understand this value is the 
> clock divider.
> 
Therefore, this place should be modified according to your previous 
suggestion.I will prepare the next version.
>>
>>
>>> +                       val |= AML_UART_BAUD_XTAL_DIV2;
>>> +               }
>>> +               val |= DIV_ROUND_CLOSEST(port->uartclk / xtal_div, 
>>> baud) - 1;
>>
>>
> 
> .