[openwrt/openwrt] airoha: backport upstream fixes for pinctrl PHY LED and MDIO
LEDE Commits
lede-commits at lists.infradead.org
Mon Nov 10 09:35:43 PST 2025
ansuel pushed a commit to openwrt/openwrt.git, branch openwrt-24.10:
https://git.openwrt.org/dc11868486deb6688a1bb2fa4b04e84ce347eae8
commit dc11868486deb6688a1bb2fa4b04e84ce347eae8
Author: Christian Marangi <ansuelsmth at gmail.com>
AuthorDate: Mon Sep 8 20:22:09 2025 +0200
airoha: backport upstream fixes for pinctrl PHY LED and MDIO
Backport fixes for Airoha pinctrl driver for PHY LED and MDIO bus. This
fix a copy-paste error for PHY LED and a misconfiguration for MT7530
embedded Switch MDIO bus GPIO pin to permit usage of external PHYs.
Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
(cherry picked from commit 35ff70e8073635d60b36875e62c9ba62b4af9182)
---
...oha-fix-wrong-PHY-LED-mux-value-for-LED1-.patch | 68 ++++++++++++++++++++++
...rl-airoha-fix-wrong-MDIO-function-bitmaks.patch | 58 ++++++++++++++++++
2 files changed, 126 insertions(+)
diff --git a/target/linux/airoha/patches-6.6/091-01-v6.18-pinctrl-airoha-fix-wrong-PHY-LED-mux-value-for-LED1-.patch b/target/linux/airoha/patches-6.6/091-01-v6.18-pinctrl-airoha-fix-wrong-PHY-LED-mux-value-for-LED1-.patch
new file mode 100644
index 0000000000..f94eab4048
--- /dev/null
+++ b/target/linux/airoha/patches-6.6/091-01-v6.18-pinctrl-airoha-fix-wrong-PHY-LED-mux-value-for-LED1-.patch
@@ -0,0 +1,68 @@
+From af87d38c442c75a40c7d0a7d8c31557e2e6ccf98 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth at gmail.com>
+Date: Sun, 25 May 2025 20:22:40 +0200
+Subject: [PATCH 1/2] pinctrl: airoha: fix wrong PHY LED mux value for LED1
+ GPIO46
+
+In all the MUX value for LED1 GPIO46 there is a Copy-Paste error where
+the MUX value is set to LED0_MODE_MASK instead of LED1_MODE_MASK.
+
+This wasn't notice as there were no board that made use of the
+secondary PHY LED but looking at the internal Documentation the actual
+value should be LED1_MODE_MASK similar to the other GPIO entry.
+
+Fix the wrong value to apply the correct MUX configuration.
+
+Cc: stable at vger.kernel.org
+Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
+Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
+---
+ drivers/pinctrl/mediatek/pinctrl-airoha.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
++++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+@@ -1746,8 +1746,8 @@ static const struct airoha_pinctrl_func_
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN3_LED0_MODE_MASK,
+- GPIO_LAN3_LED0_MODE_MASK
++ GPIO_LAN3_LED1_MODE_MASK,
++ GPIO_LAN3_LED1_MODE_MASK
+ },
+ .regmap[1] = {
+ AIROHA_FUNC_MUX,
+@@ -1810,8 +1810,8 @@ static const struct airoha_pinctrl_func_
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN3_LED0_MODE_MASK,
+- GPIO_LAN3_LED0_MODE_MASK
++ GPIO_LAN3_LED1_MODE_MASK,
++ GPIO_LAN3_LED1_MODE_MASK
+ },
+ .regmap[1] = {
+ AIROHA_FUNC_MUX,
+@@ -1874,8 +1874,8 @@ static const struct airoha_pinctrl_func_
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN3_LED0_MODE_MASK,
+- GPIO_LAN3_LED0_MODE_MASK
++ GPIO_LAN3_LED1_MODE_MASK,
++ GPIO_LAN3_LED1_MODE_MASK
+ },
+ .regmap[1] = {
+ AIROHA_FUNC_MUX,
+@@ -1938,8 +1938,8 @@ static const struct airoha_pinctrl_func_
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+- GPIO_LAN3_LED0_MODE_MASK,
+- GPIO_LAN3_LED0_MODE_MASK
++ GPIO_LAN3_LED1_MODE_MASK,
++ GPIO_LAN3_LED1_MODE_MASK
+ },
+ .regmap[1] = {
+ AIROHA_FUNC_MUX,
diff --git a/target/linux/airoha/patches-6.6/091-02-v6.18-pinctrl-airoha-fix-wrong-MDIO-function-bitmaks.patch b/target/linux/airoha/patches-6.6/091-02-v6.18-pinctrl-airoha-fix-wrong-MDIO-function-bitmaks.patch
new file mode 100644
index 0000000000..45052b405b
--- /dev/null
+++ b/target/linux/airoha/patches-6.6/091-02-v6.18-pinctrl-airoha-fix-wrong-MDIO-function-bitmaks.patch
@@ -0,0 +1,58 @@
+From 110930eb12699b92f767fc599c7ab467dd42358a Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth at gmail.com>
+Date: Tue, 8 Jul 2025 14:49:56 +0200
+Subject: [PATCH 2/2] pinctrl: airoha: fix wrong MDIO function bitmaks
+
+With further testing with an attached Aeonsemi it was discovered that
+the pinctrl MDIO function applied the wrong bitmask. The error was
+probably caused by the confusing documentation related to these bits.
+
+Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE
+is never actually set but instead it's set force enable to the 2 GPIO
+(gpio 1-2) for MDC and MDIO pin.
+
+Applying this configuration permits correct functionality of any
+externally attached PHY.
+
+Cc: stable at vger.kernel.org
+Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
+Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
+---
+ drivers/pinctrl/mediatek/pinctrl-airoha.c | 15 +++++++++------
+ 1 file changed, 9 insertions(+), 6 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
++++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
+@@ -102,6 +102,9 @@
+ #define JTAG_UDI_EN_MASK BIT(4)
+ #define JTAG_DFD_EN_MASK BIT(3)
+
++#define REG_FORCE_GPIO_EN 0x0228
++#define FORCE_GPIO_EN(n) BIT(n)
++
+ /* LED MAP */
+ #define REG_LAN_LED0_MAPPING 0x027c
+ #define REG_LAN_LED1_MAPPING 0x0280
+@@ -713,16 +716,16 @@ static const struct airoha_pinctrl_func_
+ .name = "mdio",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+- REG_GPIO_PON_MODE,
+- GPIO_SGMII_MDIO_MODE_MASK,
+- GPIO_SGMII_MDIO_MODE_MASK
+- },
+- .regmap[1] = {
+- AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GPIO_MDC_IO_MASTER_MODE_MODE,
+ GPIO_MDC_IO_MASTER_MODE_MODE
+ },
++ .regmap[1] = {
++ AIROHA_FUNC_MUX,
++ REG_FORCE_GPIO_EN,
++ FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
++ FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
++ },
+ .regmap_size = 2,
+ },
+ };
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