[openwrt/openwrt] ramips: mt7620: allow both internal and external PHYs
LEDE Commits
lede-commits at lists.infradead.org
Tue Jun 22 23:23:23 PDT 2021
981213 pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/de5394a29dae9356a830d043e76591698411e97a
commit de5394a29dae9356a830d043e76591698411e97a
Author: Michael Pratt <mcpratt at pm.me>
AuthorDate: Tue Apr 20 18:45:15 2021 -0400
ramips: mt7620: allow both internal and external PHYs
When the new variable ephy_base was introduced,
it was not applied to the if block for mdio_mode.
The first line in the mdio_mode if block
sets the EPHY base address to 12 in the SOC by writing a register,
but the corresponding variable in the driver
was still set to the default of 0.
This causes subsequent lines that write registers with the function
_mt7620_mii_write
to write to PHY addresses 0 through 4
while internal PHYs have been moved to addresses 12 through 16.
All of these lines are intended only for PHYs on the SOC internal switch,
however, they are being written to external ethernet switches
if they exist at those PHY addresses 0 through 4.
This causes some ethernet ports to be broken on boards with AR8327 or QCA8337 switch.
Other suggested fixes move those lines to the else block of mdio_mode,
but removing the else block completely also fixes it.
Therefore, move the lines to the mt7620_hw_init function main block,
and have only one instance of the function mtk_switch_w32
for writing the register with the EPHY base address.
In theory, this also allows for boards that have both external switches
and internal PHYs that lead to ethernet ports to be supported.
Fixes: 391df3782914 ("ramips: mt7620: add EPHY base mdio address changing possibility")
Signed-off-by: Michael Pratt <mcpratt at pm.me>
---
.../files/drivers/net/ethernet/ralink/gsw_mt7620.c | 119 ++++++++++-----------
1 file changed, 57 insertions(+), 62 deletions(-)
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
index 2a34e9417d..4b030f457b 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
@@ -98,12 +98,8 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
if (mdio_mode) {
- u32 val;
-
- /* turn off ephy and set phy base addr to 12 */
- mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
- (0x1f << 24) | (0xc << 16),
- GSW_REG_GPC1);
+ if (!gsw->ephy_base)
+ gsw->ephy_base = 12;
/* set MT7530 central align */
val = mt7530_mdio_r32(gsw, 0x7830);
@@ -116,64 +112,63 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
mt7530_mdio_w32(gsw, 0x7a40, val);
mt7530_mdio_w32(gsw, 0x7a78, 0x855);
- } else {
+ }
- if (gsw->ephy_base) {
- /* set phy base addr to ephy_base */
- mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
- (gsw->ephy_base << 16),
- GSW_REG_GPC1);
- fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */
- }
+ if (gsw->ephy_base) {
+ /* set phy base addr to ephy_base */
+ mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
+ (gsw->ephy_base << 16),
+ GSW_REG_GPC1);
+ fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */
+ }
- /* global page 4 */
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x4000);
-
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x7444);
- if (is_BGA)
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0114);
- else
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0117);
-
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x6212);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0777);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 29, 0x4000);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 28, 0xc077);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0000);
-
- /* global page 3 */
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x3000);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x4838);
-
- /* global page 2 */
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x2000);
- if (is_BGA) {
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0515);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0053);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aaf);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x0fad);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fc1);
- } else {
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0517);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0fd2);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aab);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x00ae);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fff);
- }
- /* global page 1 */
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x1000);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0xe7f8);
-
- /* turn on all PHYs */
- for (i = 0; i <= 4; i++) {
- val = _mt7620_mii_read(gsw, gsw->ephy_base + i, MII_BMCR);
- val &= ~BMCR_PDOWN;
- val |= BMCR_ANRESTART | BMCR_ANENABLE | BMCR_SPEED100;
- _mt7620_mii_write(gsw, gsw->ephy_base + i, MII_BMCR, val);
- }
+ /* global page 4 */
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x4000);
+
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x7444);
+ if (is_BGA)
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0114);
+ else
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0117);
+
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x6212);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0777);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 29, 0x4000);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 28, 0xc077);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0000);
+
+ /* global page 3 */
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x3000);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x4838);
+
+ /* global page 2 */
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x2000);
+ if (is_BGA) {
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0515);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0053);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aaf);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x0fad);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fc1);
+ } else {
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0517);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0fd2);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aab);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x00ae);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fff);
+ }
+ /* global page 1 */
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x1000);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0xe7f8);
+
+ /* turn on all PHYs */
+ for (i = 0; i <= 4; i++) {
+ val = _mt7620_mii_read(gsw, gsw->ephy_base + i, MII_BMCR);
+ val &= ~BMCR_PDOWN;
+ val |= BMCR_ANRESTART | BMCR_ANENABLE | BMCR_SPEED100;
+ _mt7620_mii_write(gsw, gsw->ephy_base + i, MII_BMCR, val);
}
/* global page 0 */
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