[PATCH v3 01/15] riscv: hwprobe.rst: Make indentation consistent
Guodong Xu
docular.xu at gmail.com
Wed Jun 3 04:11:56 PDT 2026
From: Andrew Jones <andrew.jones at oss.qualcomm.com>
A handful of vendor-extension entries indent continuation lines with a
tab character, while the rest of hwprobe.rst uses spaces. In addition,
many list items align their continuation lines under the 'm' of
':c:macro:' (column 7) rather than under the item text (column 4), so
the file mixes several indentation styles.
Replace the tabs with spaces and align every list item's continuation
lines under the item text, giving the whole file one consistent style.
Whitespace-only change, no functional change.
Signed-off-by: Andrew Jones <andrew.jones at oss.qualcomm.com>
[Guodong: extend from tabs->spaces to normalizing all continuation-line
indentation across the file]
Signed-off-by: Guodong Xu <docular.xu at gmail.com>
---
v3:
- Move to the front of the series.
- Extend from replacing tabs to normalizing all continuation-line
indentation, so later patches add documentation on top of a
consistent base (Andrew).
---
Documentation/arch/riscv/hwprobe.rst | 194 +++++++++++++++++------------------
1 file changed, 97 insertions(+), 97 deletions(-)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index c420a8349bc68..a09a8f16bd16f 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -82,121 +82,121 @@ The following keys are defined:
version 1.0 of the RISC-V Vector extension manual.
* :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is
- supported, as defined in version 1.0 of the Bit-Manipulation ISA
- extensions.
+ supported, as defined in version 1.0 of the Bit-Manipulation ISA
+ extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined
- in version 1.0 of the Bit-Manipulation ISA extensions.
+ in version 1.0 of the Bit-Manipulation ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
- in version 1.0 of the Bit-Manipulation ISA extensions.
+ in version 1.0 of the Bit-Manipulation ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
- ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+ ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
* :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined
- in version 1.0 of the Bit-Manipulation ISA extensions.
+ in version 1.0 of the Bit-Manipulation ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as
- defined in version 1.0 of the Scalar Crypto ISA extensions.
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as
- defined in version 1.0 of the Scalar Crypto ISA extensions.
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as
- defined in version 1.0 of the Scalar Crypto ISA extensions.
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as
- defined in version 1.0 of the Scalar Crypto ISA extensions.
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as
- defined in version 1.0 of the Scalar Crypto ISA extensions.
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as
- defined in version 1.0 of the Scalar Crypto ISA extensions.
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as
- defined in version 1.0 of the Scalar Crypto ISA extensions.
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as
- defined in version 1.0 of the Scalar Crypto ISA extensions.
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined
- in version 1.0 of the Scalar Crypto ISA extensions.
+ in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as
- defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as
- defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as
- defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as
- defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as
- defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as
- defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as
- defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as
- defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as
- defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as
- defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported
- as defined in the RISC-V ISA manual.
+ as defined in the RISC-V ISA manual.
* :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
- supported as defined in the RISC-V ISA manual.
+ supported as defined in the RISC-V ISA manual.
* :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
- is supported as defined in the RISC-V ISA manual.
+ is supported as defined in the RISC-V ISA manual.
* :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as
- defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
- ("Remove draft warnings from Zvfh[min]").
+ defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
+ ("Remove draft warnings from Zvfh[min]").
* :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as
- defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
- ("Remove draft warnings from Zvfh[min]").
+ defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
+ ("Remove draft warnings from Zvfh[min]").
* :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as
- defined in the RISC-V ISA manual starting from commit 056b6ff467c7
- ("Zfa is ratified").
+ defined in the RISC-V ISA manual starting from commit 056b6ff467c7
+ ("Zfa is ratified").
* :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as
- defined in the RISC-V ISA manual starting from commit 5618fb5a216b
- ("Ztso is now ratified.")
+ defined in the RISC-V ISA manual starting from commit 5618fb5a216b
+ ("Ztso is now ratified.")
* :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as
- defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
- from commit 5059e0ca641c ("update to ratified").
+ defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
+ from commit 5059e0ca641c ("update to ratified").
* :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0
- is supported as defined in the RISC-V ISA manual.
+ is supported as defined in the RISC-V ISA manual.
* :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as
- defined in the RISC-V Integer Conditional (Zicond) operations extension
- manual starting from commit 95cf1f9 ("Add changes requested by Ved
- during signoff")
+ defined in the RISC-V Integer Conditional (Zicond) operations extension
+ manual starting from commit 95cf1f9 ("Add changes requested by Ved
+ during signoff")
* :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is
- supported as defined in the RISC-V ISA manual starting from commit
- d8ab5c78c207 ("Zihintpause is ratified").
+ supported as defined in the RISC-V ISA manual starting from commit
+ d8ab5c78c207 ("Zihintpause is ratified").
* :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0
- is supported as defined in the RISC-V ISA manual.
+ is supported as defined in the RISC-V ISA manual.
* :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
supported, as defined by version 1.0 of the RISC-V Vector extension manual.
@@ -214,84 +214,84 @@ The following keys are defined:
supported, as defined by version 1.0 of the RISC-V Vector extension manual.
* :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is
- supported as defined in the RISC-V ISA manual starting from commit
- 58220614a5f ("Zimop is ratified/1.0").
+ supported as defined in the RISC-V ISA manual starting from commit
+ 58220614a5f ("Zimop is ratified/1.0").
* :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard
- extensions for code size reduction, as ratified in commit 8be3419c1c0
- ("Zcf doesn't exist on RV64 as it contains no instructions") of
- riscv-code-size-reduction.
+ extensions for code size reduction, as ratified in commit 8be3419c1c0
+ ("Zcf doesn't exist on RV64 as it contains no instructions") of
+ riscv-code-size-reduction.
* :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard
- extensions for code size reduction, as ratified in commit 8be3419c1c0
- ("Zcf doesn't exist on RV64 as it contains no instructions") of
- riscv-code-size-reduction.
+ extensions for code size reduction, as ratified in commit 8be3419c1c0
+ ("Zcf doesn't exist on RV64 as it contains no instructions") of
+ riscv-code-size-reduction.
* :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard
- extensions for code size reduction, as ratified in commit 8be3419c1c0
- ("Zcf doesn't exist on RV64 as it contains no instructions") of
- riscv-code-size-reduction.
+ extensions for code size reduction, as ratified in commit 8be3419c1c0
+ ("Zcf doesn't exist on RV64 as it contains no instructions") of
+ riscv-code-size-reduction.
* :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard
- extensions for code size reduction, as ratified in commit 8be3419c1c0
- ("Zcf doesn't exist on RV64 as it contains no instructions") of
- riscv-code-size-reduction.
+ extensions for code size reduction, as ratified in commit 8be3419c1c0
+ ("Zcf doesn't exist on RV64 as it contains no instructions") of
+ riscv-code-size-reduction.
* :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is
- supported as defined in the RISC-V ISA manual starting from commit
- c732a4f39a4 ("Zcmop is ratified/1.0").
+ supported as defined in the RISC-V ISA manual starting from commit
+ c732a4f39a4 ("Zcmop is ratified/1.0").
* :c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Zawrs extension is supported as
- ratified in commit 98918c844281 ("Merge pull request #1217 from
- riscv/zawrs") of riscv-isa-manual.
+ ratified in commit 98918c844281 ("Merge pull request #1217 from
+ riscv/zawrs") of riscv-isa-manual.
* :c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported as
- defined in the in the RISC-V ISA manual starting from commit e87412e621f1
- ("integrate Zaamo and Zalrsc text (#1304)").
+ defined in the in the RISC-V ISA manual starting from commit e87412e621f1
+ ("integrate Zaamo and Zalrsc text (#1304)").
* :c:macro:`RISCV_HWPROBE_EXT_ZALASR`: The Zalasr extension is supported as
- frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
+ frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
* :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as
- defined in the in the RISC-V ISA manual starting from commit e87412e621f1
- ("integrate Zaamo and Zalrsc text (#1304)").
+ defined in the in the RISC-V ISA manual starting from commit e87412e621f1
+ ("integrate Zaamo and Zalrsc text (#1304)").
* :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as
- defined in version 1.0 of the RISC-V Pointer Masking extensions.
+ defined in version 1.0 of the RISC-V Pointer Masking extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as
- defined in the RISC-V ISA manual starting from commit 4dc23d6229de
- ("Added Chapter title to BF16").
+ defined in the RISC-V ISA manual starting from commit 4dc23d6229de
+ ("Added Chapter title to BF16").
* :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as
- defined in the RISC-V ISA manual starting from commit 4dc23d6229de
- ("Added Chapter title to BF16").
+ defined in the RISC-V ISA manual starting from commit 4dc23d6229de
+ ("Added Chapter title to BF16").
* :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as
- defined in the RISC-V ISA manual starting from commit 4dc23d6229de
- ("Added Chapter title to BF16").
+ defined in the RISC-V ISA manual starting from commit 4dc23d6229de
+ ("Added Chapter title to BF16").
* :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as
- ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+ ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
* :c:macro:`RISCV_HWPROBE_EXT_ZABHA`: The Zabha extension is supported as
- ratified in commit 49f49c842ff9 ("Update to Rafified state") of
- riscv-zabha.
+ ratified in commit 49f49c842ff9 ("Update to Rafified state") of
+ riscv-zabha.
* :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as
- ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+ ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
* :c:macro:`RISCV_HWPROBE_EXT_ZILSD`: The Zilsd extension is supported as
- defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating
- load/store pair for RV32 with the main manual") of the riscv-isa-manual.
+ defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating
+ load/store pair for RV32 with the main manual") of the riscv-isa-manual.
* :c:macro:`RISCV_HWPROBE_EXT_ZCLSD`: The Zclsd extension is supported as
- defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating
- load/store pair for RV32 with the main manual") of the riscv-isa-manual.
+ defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating
+ load/store pair for RV32 with the main manual") of the riscv-isa-manual.
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
- :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
- mistakenly classified as a bitmask rather than a value.
+ :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
+ mistakenly classified as a bitmask rather than a value.
* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing
the performance of misaligned scalar native word accesses on the selected set
@@ -326,7 +326,7 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.
* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing the
- performance of misaligned vector accesses on the selected set of processors.
+ performance of misaligned vector accesses on the selected set of processors.
* :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned
vector accesses is unknown.
@@ -348,7 +348,7 @@ The following keys are defined:
* MIPS
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor
- extension is supported in the MIPS ISA extensions spec.
+ extension is supported in the MIPS ISA extensions spec.
* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the
thead vendor extensions that are compatible with the
@@ -357,8 +357,8 @@ The following keys are defined:
* T-HEAD
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor
- extension is supported in the T-Head ISA extensions spec starting from
- commit a18c801634 ("Add T-Head VECTOR vendor extension. ").
+ extension is supported in the T-Head ISA extensions spec starting from
+ commit a18c801634 ("Add T-Head VECTOR vendor extension. ").
* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
represents the size of the Zicbom block in bytes.
@@ -370,20 +370,20 @@ The following keys are defined:
* SIFIVE
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor
- extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
- Extensions Specification.
+ extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
+ Extensions Specification.
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor
- extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
- Instruction Extensions Specification.
+ extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
+ Instruction Extensions Specification.
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf
- vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged
- Clip Instructions Extensions Specification.
+ vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged
+ Clip Instructions Extensions Specification.
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
- vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
- Instruction Extensions Specification.
+ vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
+ Instruction Extensions Specification.
* :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which
represents the size of the Zicbop block in bytes.
--
2.43.0
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