[PATCH v3 00/15] riscv: hwprobe: Expose RVA23U64 base behavior
Guodong Xu
docular.xu at gmail.com
Wed Jun 3 04:11:55 PDT 2026
This series builds on Andrew Jones's earlier RFC [1]. It lets
userspace check for RVA23U64 conformance in one call, instead of
walking hwprobe + prctl across every mandatory extension.
The series adds a small framework that resolves profile-class
bases (IMA and RVA23U64) from the kernel's ISA extension bitmap at
init time, and surfaces the result through both /proc/cpuinfo and
hwprobe. Later patches can add RVA23S64, and backward RVA22 / RVA20
detection, to riscv_set_isa_bases() without changes to the
surrounding code.
Changes in v3 came from these sources:
1. A rebase from v7.1-rc2 to v7.1-rc6;
2. hwprobe.rst clean-up is moved to first;
3. Zic64b is added as a first-class ISA extension (dt-binding,
cpufeature parsing, and hwprobe export);
4. Resolve review comments from v2.
V3 Series outline:
1-3. hwprobe.rst clean-ups: normalize indentation first, then
document EXT_ZICFISS / EXT_ZICFILP, and standardize single-letter
extension capitalization.
4. Zicclsm: cpufeature parsing + hwprobe export.
5. Ziccamoa, Ziccif, Ziccrse, Za64rs: cpufeature parsing + hwprobe export.
6. B: cpuufeature pasrsing + hwprobe export, as the Zba/Zbb/Zbs set.
7. Zic64b: dt-bindings, with a schema check.
8. Zic64b: cpufeature parsing + hwprobe export.
9-11. dts: Declare zic64b in the SpacemiT K3, SpacemiT K1, and Sophgo
SG2044 device trees.
12. riscv_have_user_pmlen(): arch-level accessor for user
pointer-masking PMLEN support, used by RVA23U64 detection.
13. cpufeature: per-hart and host-wide isa_bases bitmaps,
populated at init time. IMA and RVA23U64 detection lives
here.
14. /proc/cpuinfo: print "isa bases:" and "hart isa bases:", eg. rva23u64.
15. hwprobe: expose RVA23U64.
Tested on both K3 Pico ITX and Qemu with -cpu rva23s64,sv39=on:
- /proc/cpuinfo reports "isa bases : rv64ima rva23u64" on both the
aggregated and per-hart lines.
- hwprobe RISCV_HWPROBE_KEY_BASE_BEHAVIOR returns
BASE_BEHAVIOR_IMA | BASE_BEHAVIOR_RVA23U64.
Based on v7.1-rc6 plus [2]; happy to rebase onto another tree if needed.
A branch is available for all patches in the series: [3].
Note: [2] is only required in order to save the merge effort for adding
'Zic64b' and 'Ziccrse' into the same k3.dtsi.
Link: https://lore.kernel.org/linux-riscv/20260206002349.96740-1-andrew.jones@oss.qualcomm.com/ [1]
Link: https://lore.kernel.org/all/20260602070257-KYC5031219@kernel.org/ [2]
Link: https://github.com/docularxu/linux/commits/b4/rva23u64-hwprobe/ [3]
---
Changes in v3:
- Add Zic64b as a first-class ISA extension: dt-binding, cpufeature
parsing with a validate check, hwprobe export, and device-tree
declarations for K3/K1/SG2044.
- Patch 1 is now a clean up of hwprobe.rst indentation.
- Document RISCV_HWPROBE_EXT_ZICFILP alongside ZICFISS.
- Move the Zicclsm hwprobe.rst entry to the IMA_EXT_1 section to match
its bit allocation.
- Collect Anup Patel's Acked-by/Reviewed-by on Patch 3, the capitalization.
- In cpufeature.c, set the local ext_mask with __set_bit().
- Update Guodong Xu's email to docular.xu at gmail.com.
- Link to v2: https://patch.msgid.link/20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com
Changes in v2 (since Andrew's RFC v1):
- Rebased onto v7.1-rc2.
- Reworked rva23u64 detection into per-hart and host isa_bases bitmaps,
shared by /proc/cpuinfo and hwprobe.
- Scoped to IMA and RVA23U64 (RVA23S64, RVA20/RVA22 cpuinfo output deferred).
- Link to v1: https://lore.kernel.org/linux-riscv/20260206002349.96740-1-andrew.jones@oss.qualcomm.com
BR,
Guodong Xu
To: Jonathan Corbet <corbet at lwn.net>
To: Paul Walmsley <pjw at kernel.org>
To: Palmer Dabbelt <palmer at dabbelt.com>
To: Conor Dooley <conor.dooley at microchip.com>
To: Albert Ou <aou at eecs.berkeley.edu>
To: Alexandre Ghiti <alex at ghiti.fr>
To: Shuah Khan <shuah at kernel.org>
To: Anup Patel <anup at brainfault.org>
To: Atish Patra <atish.patra at linux.dev>
To: Shuah Khan <skhan at linuxfoundation.org>
To: Deepak Gupta <debug at rivosinc.com>
To: Zong Li <zong.li at sifive.com>
To: Christian Brauner <brauner at kernel.org>
Cc: Andrew Jones <andrew.jones at oss.qualcomm.com>
Cc: Charles Jenkins <thecharlesjenkins at gmail.com>
Cc: Samuel Holland <samuel.holland at sifive.com>
Cc: linux-doc at vger.kernel.org
Cc: linux-riscv at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-kselftest at vger.kernel.org
Cc: kvm at vger.kernel.org
Cc: kvm-riscv at lists.infradead.org
Signed-off-by: Guodong Xu <docular.xu at gmail.com>
---
Andrew Jones (4):
riscv: hwprobe.rst: Make indentation consistent
riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to cpufeature and hwprobe
riscv: Add B to hwcap and hwprobe
riscv: Add a getter for user PMLEN support
Charlie Jenkins (1):
riscv: Standardize extension capitalization
Guodong Xu (9):
riscv: hwprobe.rst: Document EXT_ZICFISS and EXT_ZICFILP
dt-bindings: riscv: Add Zic64b extension description
riscv: Add Zic64b to cpufeature and hwprobe
riscv: dts: spacemit: k3: Add Zic64b ISA extension
riscv: dts: spacemit: k1: Add Zic64b ISA extension
riscv: dts: sophgo: sg2044: Add Zic64b ISA extension
riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection
riscv: cpu: Output isa bases lines in cpuinfo
riscv: hwprobe: Introduce rva23u64 base behavior
Jesse Taube (1):
riscv: Add Zicclsm to cpufeature and hwprobe
Documentation/arch/riscv/hwprobe.rst | 239 ++++++++++++---------
.../devicetree/bindings/riscv/extensions.yaml | 20 ++
arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 128 +++++------
arch/riscv/boot/dts/spacemit/k1.dtsi | 80 +++----
arch/riscv/boot/dts/spacemit/k3.dtsi | 48 ++---
arch/riscv/include/asm/cpufeature.h | 14 ++
arch/riscv/include/asm/hwcap.h | 24 ++-
arch/riscv/include/asm/processor.h | 4 +
arch/riscv/include/asm/switch_to.h | 4 +-
arch/riscv/include/uapi/asm/hwcap.h | 1 +
arch/riscv/include/uapi/asm/hwprobe.h | 10 +-
arch/riscv/kernel/cpu.c | 26 +++
arch/riscv/kernel/cpufeature.c | 182 ++++++++++++++--
arch/riscv/kernel/process.c | 12 ++
arch/riscv/kernel/sys_hwprobe.c | 34 ++-
arch/riscv/kvm/isa.c | 16 +-
arch/riscv/kvm/main.c | 2 +-
arch/riscv/kvm/vcpu_fp.c | 20 +-
arch/riscv/kvm/vcpu_onereg.c | 6 +-
arch/riscv/kvm/vcpu_vector.c | 10 +-
tools/testing/selftests/riscv/hwprobe/which-cpus.c | 2 +-
21 files changed, 586 insertions(+), 296 deletions(-)
---
base-commit: a04586b3d291a349301c2463bc485d05a3968383
change-id: 20260508-rva23u64-hwprobe-v2-1d20739cbb8e
Best regards,
--
Guodong Xu <docular.xu at gmail.com>
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