[PATCH] arm: socfpga: agilex5: define QSPI flash registers

[Michael Tretter]

After requesting direct QSPI flash access from the SDM firmware, barebox
gains memory mapped access to the QSPI flash controller.

Add the registers to the SoCfpga memory map to be able to use names
instead of registers when initializing the driver.

Signed-off-by: Michael Tretter <m.tretter at pengutronix.de>
---
 include/mach/socfpga/soc64-regs.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/mach/socfpga/soc64-regs.h b/include/mach/socfpga/soc64-regs.h
index fd8cfa17ba1b..1c1fb705526c 100644
--- a/include/mach/socfpga/soc64-regs.h
+++ b/include/mach/socfpga/soc64-regs.h
@@ -82,6 +82,8 @@
 #define SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS		0x18000800
 #define SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS		0x18000A00
 #define SOCFPGA_FW_TBU2NOC_ADDRESS		0x18000C00
+#define SOCFPGA_HPS2SDM_QSPI_REGS		0x108d2000
+#define SOCFPGA_HPS2SDM_QSPI_DATA		0x10900000
 #define SOCFPGA_FIREWALL_L4_PER_ADDRESS		0x10d21000
 #define SOCFPGA_FIREWALL_L4_PER_NAND_REG	0x0
 #define SOCFPGA_FIREWALL_L4_PER_USB0_REG	0xc

---
base-commit: 4a752d2303440195e12ed1a4e642b0be5b450b8e
change-id: 20260928-socfpga-agilex5-qspi-ec0c0b8c3afb

Best regards,
-- 
Michael Tretter <m.tretter at pengutronix.de>