[PATCH 00/11] arm: socfpga: agilex5: add xload support for bl33 to FSBL

[Sascha Hauer]

Hi Michael,

On 2026-10-07 12:55, Michael Tretter wrote:
> The image of the first stage boot loader on the Agilex 5 is limited to
> approximately 256k. The SRAM is actually 512k, but there is some handoff
> data at the send of the SRAM, which must not be overridden. There are
> some size checks, but due to compression of the FSBL image, it's the
> possible image size cannot be determined reliably.
> 
> The barebox PBL and a full featured barebox proper are easily larger
> than the allowed size. Compression of the piggy data may even be counter
> productive, since the entire FSBL image is compressed again when
> creating the boot image.
> 
> Add support to remove the piggy data from the FSBL image, and load the
> second stage (consisting of a barebox PBL and barebox proper) from flash
> in the PBL.
> 
> Patches 1-4 rework the Cadence QSPI NOR flash driver to be available in
> the PBL via the pbl_bio abstraction.
> 
> Patches 5-9 extend the Agilex 5 support to initialize the flash driver
> in the PBL and chain load an SSBL as bl33 instead of copying the
> currently running barebox. The patches also add the infrastructure to
> build the PBL without piggy data and device tree.
> 
> Patches 10-11 enable the xload support in the Arrow AXE5 Eagle board.
> 

This series currently breaks compilation on -next. socfpga-agilex5_defconfig
fails with:

../arch/arm/boards/arrow-axe5-eagle/lowlevel.c:17:23: error: 'CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE_XLOAD_ADDR' undeclared here (not in a function); did you mean 'CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE'?
   17 |         .nor_offset = CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE_XLOAD_ADDR,
      |                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      |                       CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE
../arch/arm/boards/arrow-axe5-eagle/lowlevel.c:18:21: error: 'CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE_XLOAD_SIZE' undeclared here (not in a function); did you mean 'CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE'?
   18 |         .nor_size = CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE_XLOAD_SIZE,
      |                     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      |                     CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE

xload support is currently optional and disabled, the existence of
CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE_XLOAD_ADDR depends on the xload
being enabled, but they are used unconditionally.

Could you send a fixup?

Sascha

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