[PATCH] arm: socfpga: axe5-eagle: move PHY reset to board code

[Michael Tretter]

The AXE5 Eagle low level code configures the Ethernet pinmux and PHY
reset. This code is executed in EL3 and in EL1, and the PHY reset is
toggled and waited for twice.

There is no reason to perform the pinmux and reset in the low level
code, but it actually belongs into the board code.

It would be even better to let the responsible drivers do the reset, but
due to the limited binary size, it's not possible to enable the GPIO
driver for Agilex 5 in barebox.

Signed-off-by: Michael Tretter <m.tretter at pengutronix.de>
---
 arch/arm/boards/arrow-axe5-eagle/board.c    | 23 +++++++++++++++++++++++
 arch/arm/boards/arrow-axe5-eagle/lowlevel.c | 18 ------------------
 2 files changed, 23 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boards/arrow-axe5-eagle/board.c b/arch/arm/boards/arrow-axe5-eagle/board.c
index b0c4b2034a77..b197367f45e4 100644
--- a/arch/arm/boards/arrow-axe5-eagle/board.c
+++ b/arch/arm/boards/arrow-axe5-eagle/board.c
@@ -5,8 +5,31 @@
 #include <bbu.h>
 #include <mach/socfpga/soc64-regs.h>
 
+static void axe5_ethernet_phy_reset(void)
+{
+	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x224);
+	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x228);
+	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x23c);
+	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x234);
+	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x248);
+	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x24c);
+
+	writel(0x410, 0x10c03304);
+	writel(0x410, 0x10c03300);
+	/*
+	 * reset the phy via GPIO10. We currently haven't got enough space
+	 * to enable the gpio driver in barebox.
+	 */
+	writel(0x000, 0x10c03300);
+	/* FIXME:  can this be decreased? */
+	mdelay(1000);
+	writel(0x410, 0x10c03300);
+}
+
 static int axe5_probe(struct device *dev)
 {
+	axe5_ethernet_phy_reset();
+
 	return 0;
 }
 
diff --git a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
index ffa5620413f6..316ea5219d05 100644
--- a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
+++ b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
@@ -23,24 +23,6 @@ static noinline void axe5_eagle_continue(void)
 
 	pr_debug("Lowlevel init done\n");
 
-	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x224);
-	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x228);
-	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x23c);
-	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x234);
-	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x248);
-	writel(0x14, SOCFPGA_PINMUX_ADDRESS + 0x24c);
-
-	writel(0x410, 0x10c03304);
-	writel(0x410, 0x10c03300);
-	/*
-	 * reset the phy via GPIO10. We currently haven't got enough space
-	 * to enable the gpio driver in barebox.
-	 */
-	writel(0x000, 0x10c03300);
-	/* FIXME:  can this be decreased? */
-	mdelay(1000);
-	writel(0x410, 0x10c03300);
-
 	agilex5_barebox_entry(__dtb_z_socfpga_agilex5_axe5_eagle_start);
 }
 

---
base-commit: 2cb5e0014a37160731ad6eb6d7f7d846394db362
change-id: 20260513-socfpga-axe5-phy-reset-813baf3c8d9c

Best regards,
-- 
Michael Tretter <m.tretter at pengutronix.de>