ARM: socfpga: enclustra-sa2: issue with I2C1

[David Picard]

Hello,

@Stephen and Ian: I Cc you since I spotted you authored commits related 
to Intel SoC FPGA pin muxing.

I'm trying to enable the I2C1 bus on a Cyclone V-base module, mounted on 
a base board. The I2C1 lines connect to a 2.54mm header, on which I 
attached a I²C device with pull-up resistors at address 0x40.
https://www.enclustra.com/en/products/system-on-chip-modules/mercury-sa2/

I can't detect the I²C device, nor can I see any pulse on the SCL line, 
which is constantly at +3.3V.

I changed the pin muxing in Quartus, updated the handoff files, changed 
the devicetree. The I2C1 bus is visible in Barebox and Linux. More 
detail here:
https://community.altera.com/discussions/fpga-device/cyclone-v-hps-i2c1-issue-no-activity-on-bus/352583

As documented on the Barebox website, I generated the BSP files with the 
Quartus script bsp-create-settings and copied the handoff files to the 
Barebox build directory. After that, I could see that 
iocsr_config_cyclone5.c and pinmux_config.c had changed.
https://www.barebox.org/doc/2025.05.0/boards/socfpga.html#updating-handoff-files
https://www.intel.com/content/www/us/en/docs/programmable/683187/20-1/bsp-create-settings.html

If someone could give me some hint, that would be really great!

David