[PATCH 8/9] arm: socfpga: agilex5: add agilex5_barebox_entry

[Michael Tretter]

Extract the SoC-specific lowlevel entry code from the board-specific
lowlevel entry code to make it reusable with other boards.

Signed-off-by: Michael Tretter <m.tretter at pengutronix.de>
---
 arch/arm/boards/arrow-axe5-eagle/lowlevel.c | 40 +----------------------------
 arch/arm/mach-socfpga/atf.c                 | 40 ++++++++++++++++++++++++++++-
 include/mach/socfpga/generic.h              |  2 +-
 3 files changed, 41 insertions(+), 41 deletions(-)

diff --git a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
index 4817b3ec2d86..fae542e11e89 100644
--- a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
+++ b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
@@ -8,11 +8,6 @@
 #include <mach/socfpga/debug_ll.h>
 #include <mach/socfpga/init.h>
 #include <mach/socfpga/generic.h>
-#include <mach/socfpga/mailbox_s10.h>
-#include <mach/socfpga/soc64-firewall.h>
-#include <mach/socfpga/soc64-regs.h>
-#include <mach/socfpga/soc64-sdram.h>
-#include <mach/socfpga/soc64-system-manager.h>
 
 extern char __dtb_z_socfpga_agilex5_axe5_eagle_start[];
 
@@ -20,10 +15,6 @@ extern char __dtb_z_socfpga_agilex5_axe5_eagle_start[];
 
 static noinline void axe5_eagle_continue(void)
 {
-	void *fdt;
-	phys_addr_t membase;
-	phys_size_t memsize;
-
 	agilex5_clk_init();
 
 	socfpga_uart_setup_ll();
@@ -49,36 +40,7 @@ static noinline void axe5_eagle_continue(void)
 	mdelay(1000);
 	writel(0x410, 0x10c03300);
 
-	if (current_el() == 3) {
-		agilex5_initialize_security_policies();
-		pr_debug("Security policies initialized\n");
-
-		/*
-		 * need to set the bank select enable before the
-		 * agilex5_ddr_init_full() otherwise the serial doesn't show
-		 * anything.
-		 */
-		if (!IS_ENABLED(CONFIG_DEBUG_LL))
-			writel(LCR_BKSE, SOCFPGA_UART0_ADDRESS + LCR);
-		agilex5_ddr_init_full();
-
-		socfpga_mailbox_s10_init();
-		socfpga_mailbox_s10_qspi_open();
-
-		agilex5_load_and_start_image_via_tfa();
-	}
-
-	fdt = __dtb_z_socfpga_agilex5_axe5_eagle_start;
-
-	membase = agilex5_mpfe_sdram_base();
-	memsize = agilex5_mpfe_sdram_size();
-
-	if (membase < SOCFPGA_AGILEX5_DDR_BASE || memsize == 0) {
-		pr_err("Invalid firewall configuration\n");
-		hang();
-	}
-
-	barebox_arm_entry(membase, memsize, fdt);
+	agilex5_barebox_entry(__dtb_z_socfpga_agilex5_axe5_eagle_start);
 }
 
 ENTRY_FUNCTION_WITHSTACK(start_socfpga_agilex5_axe5_eagle, AXE5_STACKTOP, r0, r1, r2)
diff --git a/arch/arm/mach-socfpga/atf.c b/arch/arm/mach-socfpga/atf.c
index 3ad19e33ac94..e3461d01174e 100644
--- a/arch/arm/mach-socfpga/atf.c
+++ b/arch/arm/mach-socfpga/atf.c
@@ -7,9 +7,12 @@
 #include <asm/barebox-arm.h>
 #include <mach/socfpga/atf.h>
 #include <mach/socfpga/generic.h>
+#include <mach/socfpga/mailbox_s10.h>
 #include <mach/socfpga/soc64-regs.h>
+#include <mach/socfpga/soc64-sdram.h>
+#include <mach/socfpga/soc64-system-manager.h>
 
-void __noreturn agilex5_load_and_start_image_via_tfa(void)
+static void __noreturn agilex5_load_and_start_image_via_tfa(void)
 {
 	void *bl31 = (void *)AGILEX5_ATF_BL31_BASE_ADDR;
 	void *bl33 = (void *)AGILEX5_ATF_BL33_BASE_ADDR;
@@ -33,3 +36,38 @@ void __noreturn agilex5_load_and_start_image_via_tfa(void)
 	bl31_entry((uintptr_t)bl31, 0, (uintptr_t)bl33, 0);
 	__builtin_unreachable();
 }
+
+void __noreturn agilex5_barebox_entry(void *fdt)
+{
+	phys_addr_t membase;
+	phys_size_t memsize;
+
+	if (current_el() == 3) {
+		agilex5_initialize_security_policies();
+		pr_debug("Security policies initialized\n");
+
+		/*
+		 * need to set the bank select enable before the
+		 * agilex5_ddr_init_full() otherwise the serial doesn't show
+		 * anything.
+		 */
+		if (!IS_ENABLED(CONFIG_DEBUG_LL))
+			writel(LCR_BKSE, SOCFPGA_UART0_ADDRESS + LCR);
+		agilex5_ddr_init_full();
+
+		socfpga_mailbox_s10_init();
+		socfpga_mailbox_s10_qspi_open();
+
+		agilex5_load_and_start_image_via_tfa();
+	}
+
+	membase = agilex5_mpfe_sdram_base();
+	memsize = agilex5_mpfe_sdram_size();
+
+	if (membase < SOCFPGA_AGILEX5_DDR_BASE || memsize == 0) {
+		pr_err("Invalid firewall configuration\n");
+		hang();
+	}
+
+	barebox_arm_entry(membase, memsize, fdt);
+}
diff --git a/include/mach/socfpga/generic.h b/include/mach/socfpga/generic.h
index 06768e9ec0a0..6c99a17e81f1 100644
--- a/include/mach/socfpga/generic.h
+++ b/include/mach/socfpga/generic.h
@@ -100,7 +100,7 @@ static inline void arria10_watchdog_disable(void) {}
 #endif
 
 int agilex5_clk_init(void);
-void __noreturn agilex5_load_and_start_image_via_tfa(void);
+void __noreturn agilex5_barebox_entry(void *fdt);
 
 static inline void __udelay(unsigned us)
 {

-- 
2.47.3