[PATCH] ARM: i.MX7: DDR size detection off-by-one in row_max

[Anees Rehman]

The imx7d_ddrc_sdram_size() function passes row_max=15 to
imx_ddrc_sdram_size(), but the correct value is 16. This causes
count_bits() to return one less than the actual number of row
address bits, halving the detected memory size for any i.MX7D
configuration with 14 row addresses (e.g. 4Gbit LPDDR2).

For example, with 14 row address pins (R0-R13), ADDRMAP6 disables
row bits 14 and 15. count_bits(15, ...) returns 15-2=13 instead
of the correct 14, resulting in 256MB detected instead of 512MB
(single rank) or 512MB instead of 1GB (dual rank).

Fixes: 2639f77c8a45 ("ARM: i.MX: esdctl: Add memory size detection for i.MX7D")
Signed-off-by: Anees Rehman <anees.r3hman at gmail.com>
---
 arch/arm/mach-imx/esdctl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 6dc92e90fc..05c355accc 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -642,7 +642,7 @@ static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc)
 
 	return imx_ddrc_sdram_size(ddrc, addrmap,
 				   11, ARRAY_AND_SIZE(col_b),
-				   15, ARRAY_AND_SIZE(row_b),
+				   16, ARRAY_AND_SIZE(row_b),
 				   reduced_adress_space, mstr);
 }
 
-- 
2.53.0