[PATCH] ARM: ARMv5: make PTE_SMALL_AP_UNO_SRO work

[Ahmad Fatoum]

On 4/2/26 4:01 PM, Sascha Hauer wrote:
> On ARMv4/5 we have the SCTLR.S and SCTLR.R bits. We set the former which
> is deprecated and has implementation defined behaviour on ARMv5. We
> clear the latter which has the effect that AP=0b00 as used in PTE_SMALL_AP_UNO_SRO
> means "no access".
> 
> Clear SCTLR.S and set SCTLR.R instead. With this AP=0b00 maps to
> read-only access as intended.
> 
> Do not touch any of these bits for >= ARMv6 as both are reserved there.
> 
> Fixes: 5916385fae ("ARM: MMU: map text segment ro and data segments execute never")
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>

Reviewed-by: Ahmad Fatoum <a.fatoum at pengutronix.de>

> ---
>  arch/arm/cpu/lowlevel_32.S | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/lowlevel_32.S b/arch/arm/cpu/lowlevel_32.S
> index 3b1dea5c67..517cefa7b4 100644
> --- a/arch/arm/cpu/lowlevel_32.S
> +++ b/arch/arm/cpu/lowlevel_32.S
> @@ -59,7 +59,7 @@ THUMB(	orr	r12, r12, #PSR_T_BIT	)
>  	/* disable MMU stuff and data/unified caches */
>  	mrc	p15, 0, r12, c1, c0, 0		/* SCTLR */
>  	bic	r12, r12, #(CR_M | CR_C | CR_B)
> -	bic	r12, r12, #(CR_S | CR_R | CR_V)
> +	bic	r12, r12, #CR_V
>  
>  #ifndef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
>  	/* enable instruction cache */
> @@ -70,7 +70,8 @@ THUMB(	orr	r12, r12, #PSR_T_BIT	)
>  	orr	r12, r12, #CR_U
>  	bic	r12, r12, #CR_A
>  #else
> -	orr	r12, r12, #CR_S
> +	bic	r12, r12, #CR_S
> +	orr	r12, r12, #CR_R
>  	orr	r12, r12, #CR_A
>  #endif
>  

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