[PATCH] clk: rockchip: Fix CPLL setup on RK3588

[Sascha Hauer]

On Mon, 29 Sep 2025 15:32:39 +0300, Alexander Shiyan wrote:
> This patch fixes the CPLL clock setup issue on RK3588 SoCs by temporarily
> disabling the PLL source during PLL configuration. The fix is ported from
> Rockchip's U-Boot implementation [1].
> 
> The issue occurs because CPLL requires its source to be disabled during
> configuration. We temporarily set the corresponding bit in the CRU
> register before PLL setup and restore it afterwards [2].
> 
> [...]

Applied, thanks!

[1/1] clk: rockchip: Fix CPLL setup on RK3588
      https://git.pengutronix.de/cgit/barebox/commit/?id=8b01023c3c7c (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer at pengutronix.de>